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MC68HC705JJ7/D REV 4
68HC05M6 HC05M68HC 5M68HC05M
MC68HC705JJ7 MC68HC705JP7 MC68HC705SJ7 MC68HC705SP7 MC68HRC705JJ7 MC68HRC705JP7
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HCMOS Microcontroller Unit
blank
MC68HC705JJ7 MC68HC705SJ7 MC68HRC705JJ7
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MC68HRC705SJ7 MC68HC705JP7 MC68HC705SP7
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc.
(c) Motorola, Inc., 2001
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/mcu/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date Revision Level Description General reformat to bring document up to current publication standards References to MC68HRC705SJ7 and MC68HRC705SP7 removed throughout Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit -- Change label of register $1FF0 from mask option register to COP register Table 7-2. Port B Pin Functions -- PB0-PB4 -- Change heading under Comparator 1 from OPT in MOR to OPT in COPR 12.4 PEPROM Programming -- Contact information updated August, 2001 4 Figure 13-3. EPROM Security in COP and Security Register (COPR) -- Figure title change 13.4 EPROM Programming -- Contact information updated and corrected reference to COP register from COP to COPR 15.15 SIOP Timing (VDD = 5.0 Vdc) -- Value change for clock (SCK) low time 15.16 SIOP Timing (VDD = 3.0 Vdc) -- Value change for clock (SCK) low time Section 15. Electrical Specifications -- Added Figure 15-1 through Figure 15-10 and Figure 15-12 Page Number(s) All All 94 96 179 188 189 225 226 213, 214, 219, 223, and 227
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MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
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List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 23 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 45 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Section 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . 75 Section 7. Parallel Input/Output . . . . . . . . . . . . . . . . . . . . 83 Section 8. Analog Subsystem . . . . . . . . . . . . . . . . . . . . 107 Section 9. Simple Synchronous Serial Interface . . . . . 141 Section 10. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Section 11. Programmable Timer . . . . . . . . . . . . . . . . . 159 Section 12. Personality EPROM (PEPROM) . . . . . . . . . 175 Section 13. EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . 183 Section 14. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 191 Section 15. Electrical Specifications. . . . . . . . . . . . . . . 209
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List of Sections
Section 16. Mechanical Specifications . . . . . . . . . . . . . 231 Section 17. Ordering Information . . . . . . . . . . . . . . . . . 237
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Table of Contents
Section 1. General Description
1.1 1.2 1.3 1.4 1.5 1.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VDD and VSS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7 OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.5 Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . 31 1.8 1.9 1.10 1.11 1.12 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PA0-PA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PB0-PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PC0-PC7 (MC68HC705JP7) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Section 2. Memory
2.1 2.2 2.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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2.4 2.5 2.6 2.7 2.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 User and Interrupt Vector Mapping. . . . . . . . . . . . . . . . . . . . . . 42 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . 42 Erasable Programmable Read-Only Memory (EPROM) . . . . . 43 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Section 3. Central Processor Unit (CPU)
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Section 4. Interrupts
4.1 4.2 4.3 4.4 4.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.6.1 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6.2 PA0-PA3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6.3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . 58
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4.7 Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7.1 Core Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . 60 4.7.2 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8 Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 61 4.8.1 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.8.2 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.8.3 Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9 Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.10 Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.10.1 Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . .63 4.10.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 5. Resets
5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . 68 5.5.3 Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 5.6 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.2 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.3 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.4 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.6.5 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6.7 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6.8 External Oscillator and Internal Low-Power Oscillator . . . . . 73
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Section 6. Operating Modes
6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.4 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Section 7. Parallel Input/Output
7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.3 Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.4 Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3.5 Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.3 Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.4 Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.5 PB0, PBI, PB2, and PB3 Logic. . . . . . . . . . . . . . . . . . . . . . .93 7.4.6 PB4/AN4/TCMP/CMP1 Logic. . . . . . . . . . . . . . . . . . . . . . . . 94 7.4.7 PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.4.8 PB6/SDI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4.9 PB7/SCK Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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7.5 Port C (28-Pin Versions Only) . . . . . . . . . . . . . . . . . . . . . . . . 101 7.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.5.3 Port C Pulldown Devices . . . . . . . . . . . . . . . . . . . . . . . . . .103 7.5.4 Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6 Port Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Section 8. Analog Subsystem
8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Analog Multiplex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Analog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.7 Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . . 132 8.7.1 Absolute Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . . 133 8.7.1.1 Internal Absolute Reference . . . . . . . . . . . . . . . . . . . . . 133 8.7.1.2 External Absolute Reference . . . . . . . . . . . . . . . . . . . . . 134 8.7.2 Ratiometric Voltage Readings . . . . . . . . . . . . . . . . . . . . . . 134 8.7.2.1 Internal Ratiometric Reference . . . . . . . . . . . . . . . . . . .135 8.7.2.2 External Ratiometric Reference . . . . . . . . . . . . . . . . . . . 136 8.8 Voltage Comparator Features . . . . . . . . . . . . . . . . . . . . . . . . 136 8.8.1 Voltage Comparator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.8.2 Voltage Comparator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.9 8.10 8.11 8.12 8.13 8.14 8.15 Current Source Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Internal Temperature Sensing Diode Features. . . . . . . . . . . . 138 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Port B Interaction with Analog Inputs . . . . . . . . . . . . . . . . . . .139 Port B Pins as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Port B Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Noise Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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Section 9. Simple Serial Interface
9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 9.4.1 SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . 145 9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Section 10. Core Timer
10.1 10.2 10.3 10.4 10.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Core Timer Status and Control Register. . . . . . . . . . . . . . . . . 153 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . 155 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Section 11. Programmable Timer
11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Alternate Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Timer Operation during Wait Mode. . . . . . . . . . . . . . . . . . . . . 173
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11.10 Timer Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . 173 11.11 Timer Operation during Halt Mode . . . . . . . . . . . . . . . . . . . . . 173
Section 12. Personality EPROM (PEPROM)
12.1 12.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.3.1 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . 177 12.3.2 PEPROM Status and Control Register. . . . . . . . . . . . . . . . 178 12.4 12.5 12.6 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 PEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Section 13. EPROM/OTPROM
13.1 13.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
13.3 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 13.3.1 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . 184 13.3.2 Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 13.3.3 EPROM Security Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.4 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.1 MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.2 EPMSEC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.5 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Section 14. Instruction Set
14.1 14.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
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14.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 14.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 14.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . 195 14.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 196 14.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.5 14.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Section 15. Electrical Specifications
15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 211 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . . 215 DC Electrical Characteristics (3.0 Vdc). . . . . . . . . . . . . . . . . . 216
15.10 Analog Subsystem Characteristics (5.0 Vdc) . . . . . . . . . . . . . 217
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15.11 Analog Subsystem Characteristics (3.0 Vdc) . . . . . . . . . . . . . 218 15.12 Control Timing (5.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 15.13 Control Timing (3.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 15.14 PEPROM and EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.15 SIOP Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.16 SIOP Timing (VDD = 3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.17 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Section 16. Mechanical Specifications
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 20-Pin Plastic Dual In-Line Package (Case 738) . . . . . . . . . . 232 20-Pin Small Outline Integrated Circuit (Case 751D) . . . . . . . 233 28-Pin Plastic Dual In-Line Package (Case 710) . . . . . . . . . . 233 28-Pin Small Outline Integrated Circuit (Case 751F) . . . . . . . 234 20-Pin Windowed Ceramic Integrated Circuit (Case 732) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 28-Pin Windowed Ceramic Integrated Circuit (Case 733A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Section 17. Ordering Information
17.1 17.2 17.3 17.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 MC68HC705JJ7 Order Numbers . . . . . . . . . . . . . . . . . . . . . . 238 MC68HC705JP7 Order Numbers . . . . . . . . . . . . . . . . . . . . . .239
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List of Figures
Figure 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 5-1 5-2 6-1 6-2
Title
Page
User Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 User Mode Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 EPO Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Vector Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 COP and Security Register (COPR). . . . . . . . . . . . . . . . . . . . . 43 68HC05 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 External Interrupt Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . . 58 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 COP and Security Register (COPR). . . . . . . . . . . . . . . . . . . . . 69 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . . 76 Stop/Wait/Halt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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Figure 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 9-1 9-2 9-3 9-4 9-5 9-6
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Title
Page
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . 85 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . 86 Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . 90 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . 91 Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PB0-PB3 Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 PB4/AN4/TCMP/CMP1 Pin I/O Circuit . . . . . . . . . . . . . . . . . . . 94 PB5/SDO Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 PB6/SDI Pin I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PB7/SCK Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Port C Data Register (PORTC). . . . . . . . . . . . . . . . . . . . . . . . 102 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 103 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Analog Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . 109 Analog Multiplex Register (AMUX) . . . . . . . . . . . . . . . . . . . . . 110 Comparator 2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 INV Bit Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Analog Control Register (ACR). . . . . . . . . . . . . . . . . . . . . . . . 115 Analog Status Register (ASR) . . . . . . . . . . . . . . . . . . . . . . . . 119 Single-Slope A/D Conversion Method . . . . . . . . . . . . . . . . . . 122 A/D Conversion -- Full Manual Control (Mode 0) . . . . . . . . . 128 A/D Conversion -- Manual/Auto Discharge Control (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A/D Conversion -- TOF/ICF Control (Mode 2) . . . . . . . . . . . . 130 A/D Conversion -- OCF/ICF Control (Mode 3). . . . . . . . . . . . 131 COP and Security Register (COPR). . . . . . . . . . . . . . . . . . . . 137 SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SIOP Timing Diagram (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 143 SIOP Timing Diagram (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 144 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . 145 SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . 148 SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Figure 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 12-1 12-2 12-3 13-1 13-2 13-3 15-1
Title
Page
Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Core Timer Status and Control Register (CTSCR). . . . . . . . . 153 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . . . 155 COP and Security Register (COPR). . . . . . . . . . . . . . . . . . . . 156 Programmable Timer Overall Block Diagram . . . . . . . . . . . . . 161 Programmable Timer Block Diagram . . . . . . . . . . . . . . . . . . .162 Programmable Timer Registers (TMRH and TMRL) . . . . . . . 163 Alternate Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . .164 Alternate Counter Registers (ACRH and ACRL) . . . . . . . . . . 165 Timer Input Capture Block Diagram . . . . . . . . . . . . . . . . . . . . 166 Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . .166 Timer Output Compare Block Diagram. . . . . . . . . . . . . . . . . . 168 Output Compare Registers (OCRH and OCRL) . . . . . . . . . . . 168 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . 170 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . 172 Personality EPROM Block Diagram . . . . . . . . . . . . . . . . . . . . 176 PEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . . . . 177 PEPROM Status and Control Register (PESCR) . . . . . . . . . . 178 EPROM Programming Register (EPROG) . . . . . . . . . . . . . . .184 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . 186 EPROM Security in COP and Security Register (COPR). . . . 188
Typical Run IDD versus Internal Clock Frequency at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . 213 15-2 Typical Wait IDD versus Internal Clock Frequency at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . 213 15-3 Typical Run IDD with External Oscillator . . . . . . . . . . . . . . . . . 214 15-4 Typical Wait IDD with External Oscillator . . . . . . . . . . . . . . . . 214 15-5 Typical Stop IDD with Analog and LVR Disabled . . . . . . . . . . 214 15-6 Typical Temperature Diode Performance. . . . . . . . . . . . . . . . 219 15-7 Typical 500 kHz External Low-Power Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
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Figure 15-8 15-9 Title Page
15-10
15-11 15-12 15-13 15-14 15-15
Typical 100 kHz External Low-Power Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Typical RC Oscillator Internal Operating Frequency Range versus Resistance for High VDD Operating Range at T = 25 C . . . . . . . . . . . . . . . . . . . . . .223 Typical RC Oscillator Internal Operating Frequency Range versus Resistance for Low VDD Operating Range at T = 25 C . . . . . . . . . . . . . . . . . . . . . .223 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Typical Falling Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . 227 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 228 Internal Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 228 Low-Voltage Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . 229
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List of Tables
Table 1-1 4-1 4-2 6-1 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 9-1 10-1 10-2 11-1 12-1
Title
Page
Device Options by Part Number . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset/Interrupt Vector Addresses. . . . . . . . . . . . . . . . . . . . . . .52 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port B Pin Functions -- PB0-PB4 . . . . . . . . . . . . . . . . . . . . . . 96 Port B Pin Functions -- PB5-PB7 . . . . . . . . . . . . . . . . . . . . . 101 Port C Pin Functions (28-Pin Versions Only) . . . . . . . . . . . . . 104 Comparator 2 Input Sources. . . . . . . . . . . . . . . . . . . . . . . . . . 111 Channel Select Bus Combinations . . . . . . . . . . . . . . . . . . . . . 114 A/D Conversion Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 A/D Conversion Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Sample Conversion Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . 127 Absolute Voltage Reading Errors . . . . . . . . . . . . . . . . . . . . . .134 Ratiometric Voltage Reading Errors . . . . . . . . . . . . . . . . . . . . 135 Voltage Comparator Setup Conditions . . . . . . . . . . . . . . . . . . 136 SIOP Clock Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Core Timer Interrupt Rates and COP Timeout Selection . . . . 155 COP Watchdog Recommendations . . . . . . . . . . . . . . . . . . . . 157 Output Compare Initialization Example . . . . . . . . . . . . . . . . . 169 PEPROM Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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Table 14-1 14-2 14-3 14-4 14-5 14-6 14-7 Title Page
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 195 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 196 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 198 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 199 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
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Section 1. General Description
1.1 Contents
1.2 1.3 1.4 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VDD and VSS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7 OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.5 Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . 31 1.8 1.9 1.10 1.11 1.12 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PA0-PA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PB0-PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PC0-PC7 (MC68HC705JP7) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2 Introduction
The Motorola MC68HC705JJ7 and MC68HC705JP7 are erasable programmable read-only memory (EPROM) versions of the MC68HC05JJ/JP Family of microcontrollers (MCU).
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA General Description
Advance Information 23
General Description
1.3 Features
Features of the two parts include: * * * * * * * * Low-cost, M68HC05 core MCU in 20-pin package (MC68HC705JJ7) or 28-pin package (MC68HC705JP7) 6160 bytes of user EPROM, including 16 bytes of user vectors 224 bytes of low-power user random-access memory (RAM) 64 bits of personality EPROM (serial access) 16-bit programmable timer with input capture and output compare 15-stage core timer, including 8-bit free-running counter and 4-stage selectable real-time interrupt generator Simple serial input/output port (SIOP) with interrupt capability Two voltage comparators, one of which can be combined with the 16-bit programmable timer to create a 4-channel, single-slope analog-to-digital (A/D) converter Output of voltage comparator can drive port pin PB4 directly under software control 14 input/output (I/O) lines (MC68HC705JJ7) or 22 I/O lines (MC68HC705JP7), including high-source/sink current capability on 6 I/O pins (MC68HC705JJ7) or 14 I/O pins (MC68HC705JP7) Programmable 8-bit mask option register (MOR) to select mask options found in read-only memory (ROM) based versions MOR selectable software programmable pulldowns on all I/O pins and keyboard scan interrupt on four I/O pins Software mask and request bit for IRQ interrupt with MOR selectable sensitivity on IRQ interrupt (edge- and level-sensitive or edge-only) On-chip oscillator with device option of crystal/ceramic resonator or resistor-capacitor (RC) operation and MOR selectable shunt resistor, 2 M by design
* *
* * *
*
Advance Information 24 General Description
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
General Description Device Options
* * * *
Internal oscillator for lower-power operation, approximately 100 kHz (500 kHz selected as device option) EPROM security bit(1) to aid in locking out access to programmable EPROM array MOR selectable computer operating properly (COP) watchdog system Power-saving stop and wait mode instructions (MOR selectable STOP conversion to halt and option for fast 16-cycle restart and power-on reset) On-chip temperature measurement diode MOR selectable reset module to reset central processor unit (CPU) in low-voltage conditions Illegal address reset Internal steering diode and pullup device on RESET pin to VDD
* * * *
1.4 Device Options
These MC68HC705JJ7/MC68HC705JP7 device options are available: * * On-chip oscillator type: crystal/ceramic resonator connections or resistor-capacitor (RC) connections Nominal frequency of internal low-power oscillator: 100 or 500 kHz
NOTE:
A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. The exact values and their tolerance or limits are specified in Section 15. Electrical Specifications.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA General Description
Advance Information 25
General Description
Combinations of the various device options are specified by part number. Refer to Table 1-1 and to Section 17. Ordering Information for specific ordering information. Table 1-1. Device Options by Part Number
Part Number MC68HC705JJ7 MC68HC705JP7 MC68HC705SJ7 MC68HC705SP7 MC68HRC705JJ7 MC68HRC705JP7 Pin Count 20 28 20 28 20 28 Oscillator Type Crystal/resonator Crystal/resonator Crystal/resonator Crystal/resonator Resistor-capacitor Resistor-capacitor Internal LPO Nominal Frequency (kHz) 100 100 500 500 100 100
Advance Information 26 General Description
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
General Description Device Options
OSC1 OSC2
TRANSFER CONTROL
EXTERNAL OSCILLATOR INTERNAL OSCILLATOR /2
+ COMP1 - + COMP2 -
VDD
CURRENT SOURCE
VDD
LVR
INT
16-BIT TIMER (1) INPUT CAPTURE (1) OUTPUT COMPARE 15-STAGE CORE TIMER SYSTEM WATCHDOG & ILLEGAL ADDR DETECT
TCAP TCMP ICF OCF TOF
COMPARATOR CONTROL & MULTIPLEXER
TEMPERATURE DIODE
VSS VSS VSS RESET IRQ/VPP ACCUM CPU REGISTERS INDEX REG 0 0 0 0 0 0 0 0 1 1 STK PTR INT PROGRAM COUNTER COND CODE REG 11 1H I NZC PORT A DATA DIR. REG. SIMPLE SERIAL INTERFACE (SIOP) PA5* PA4* PORT A PA3* PA2* PA1* PA0* PC7* PORT C DATA DIR. REG. PC6* PC5* PORT C PC4* PC3* PC2* PC1* PC0* PORT C ONLY ON 28-PIN VERSIONS CPU CONTROL 68HC05 CPU ALU INT PB0/AN0 PORT B DATA DIR. REG. PB1/AN1 PB2/AN2 PORT B PB3/AN3/TCAP PB4/AN4/TCMP/CMP1* PB5/SDO PB6/SDI PB7/SCK
BOOT ROM -- 240 BYTES STATIC RAM (4T) -- 224 BYTES
USER EPROM -- 6160 BYTES PERSONALITY EPROM -- 64 BITS
* High sink current capability * High source current capability IRQ interrupt capability
Figure 1-1. User Mode Block Diagram
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA General Description Advance Information 27
General Description
1.5 Functional Pin Description
Refer to Figure 1-2 for the pinouts of the MC68HC705JJ7 and MC68HC705JP7 in the user mode. The following paragraphs give a description of the general function of each pin.
MC68HC705JJ7
PB1/AN1 PB2/AN2 PB3/AN3/TCAP *PB4/AN4/TCMP/CMP1 PB5/SDO PB6/SDI PB7/SCK *PA5 * PA4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PB0/AN0 VDD VSS OSC1 OSC2 RESET IRQ/VPP PA0* PA1* PA2*
* PA3
MC68HC705JP7
PB1/AN1 PB2/AN2 PB3/AN3/TCAP *PB4/AN4/TCMP/CMP1 PB5/SDO * PC4 *PC5 * PC6 *PC7 PB6/SDI PB7/SCK *PA5 * PA4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB0/AN0 VDD VSS OSC1 OSC2 PC3* PC2* PC1* PC0* RESET IRQ/VPP PA0* PA1* PA2*
* PA3
* Denotes 10 mA sink /5 mA source capability Denotes IRQ interrupt capability
Figure 1-2. User Mode Pinouts
Advance Information 28 General Description
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
General Description VDD and VSS Pins
1.6 VDD and VSS Pins
Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible.
1.7 OSC1 and OSC2 Pins
The OSC1 and OSC2 pins are the connections for the external pin oscillator (EPO). The OSC1 and OSC2 pins can accept these sets of components: * * * * A crystal as shown in Figure 1-3 (a) A ceramic resonator as shown in Figure 1-3 (a) An external resistor as shown in Figure 1-3 (b) An external clock signal as shown in Figure 1-3 (c)
The selection of the crystal/ceramic resonator or RC oscillator configuration is done by product part number selection as described in Section 17. Ordering Information. The frequency, fOSC, of the EPO or external clock source is divided by two to produce the internal operating frequency, fOP.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA General Description
Advance Information 29
General Description
MCU 2 M OSC1 OSC2 OSC1
MCU
MCU
OSC2 R
OSC1
OSC2
UNCONNECTED
EXTERNAL CLOCK
(a) Crystal or Ceramic Resonator Connections
(b) RC Oscillator Connections
(c) External Clock Source Connection
Figure 1-3. EPO Oscillator Connections
1.7.1 Crystal Oscillator The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 M can be provided between OSC1 and OSC2 for the crystal type oscillator by use of the OSCRES bit in the MOR.
1.7.2 Ceramic Resonator Oscillator In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit in Figure 1-3 (a) can be used for a ceramic resonator. The resonator manufacturer's recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor
Advance Information 30 General Description MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
General Description OSC1 and OSC2 Pins
of approximately 2 M can be provided between OSC1 and OSC2 for the ceramic resonator type oscillator by use of the OSCRES bit in the MOR.
1.7.3 RC Oscillator The lowest cost oscillator is the RC oscillator configuration where a resistor is connected between the two oscillator pins as shown in Figure 1-3 (b). The selection of the RC oscillator configuration is done by product part number selection as described in Section 17. Ordering Information.
NOTE:
Do not use the internal startup resistor between OSC1 and OSC2 for the RC-type oscillator.
1.7.4 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3 (c). This oscillator can be selected via software. This configuration is possible regardless of whether the crystal/ceramic resonator or RC oscillator configuration is used.
NOTE:
Do not use the internal startup resistor between OSC1 and OSC2 for the external clock.
1.7.5 Internal Low-Power Oscillator An internal low-power oscillator (LPO) is provided which is the default oscillator out of reset. When operating from this internal LPO, the other oscillator can be powered down by software to further conserve power. The selection of the LPO configuration is done by product part number selection as described in Section 17. Ordering Information.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA General Description
Advance Information 31
General Description
1.8 RESET Pin
The RESET pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state. It also functions as an output to indicate that an internal COP watchdog, illegal address, or low-voltage reset has occurred. The RESET pin contains a pullup device to allow the pin to be left disconnected without an external pullup resistor. The RESET pin also contains a steering diode that, when the power is removed, will discharge to VDD any charge left on an external capacitor connected between the RESET pin and VSS. The RESET pin also contains an internal Schmitt trigger to improve its noise immunity as an input.
1.9 IRQ/VPP Pin
The IRQ/VPP input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function uses the LEVEL bit in the MOR to provide either negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the LEVEL bit is set to enable level-sensitive triggering, the IRQ/VPP pin requires an external resistor to VDD for "wired-OR" operation. If the IRQ/VPP pin is not used, it must be tied to the VDD supply. The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin may affect operation if the voltage on the IRQ/VPP pin is above VDD when the device is released from a reset condition. The IRQ/VPP pin should only be taken above VDD to program an EPROM memory location or personality EPROM bit. For more information, refer to 15.14 PEPROM and EPROM Programming Characteristics.
NOTE:
Each of the PA0-PA3 I/O pins may be connected as an OR function with the IRQ interrupt function by the PIRQ bit in the MOR. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ/VPP pin, except that active transitions and levels are inverted. The edge or level sensitivity selected by the LEVEL bit in the MOR for the IRQ/VPP pin also applies to the I/O
Advance Information 32 General Description
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
General Description PA0-PA5
pins that are ORed to create the IRQ signal. For more information, refer to 4.6 External Interrupts.
1.10 PA0-PA5
These six I/O lines comprise port A, a general-purpose bidirectional I/O port. This port also has four pins which have keyboard interrupt capability. All six of these pins have high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the MOR.
1.11 PB0-PB7
These eight I/O lines comprise port B, a general-purpose bidirectional I/O port. This port is also shared with the 16-bit programmable timer input capture and output compare functions, with the two voltage comparators in the analog subsystem, and with the simple serial interface (SIOP). The outputs of voltage comparator 1 can directly drive the PB4 pin; and the PB4 pin has high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the MOR.
1.12 PC0-PC7 (MC68HC705JP7)
These eight I/O lines comprise port C, a general-purpose bidirectional I/O port. This port is only available on the 28-pin MC68HC705JP7. All eight of these pins have high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the MOR.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA General Description
Advance Information 33
General Description
Advance Information 34 General Description
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 2. Memory
2.1 Contents
2.2 2.3 2.4 2.5 2.6 2.7 2.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 User and Interrupt Vector Mapping. . . . . . . . . . . . . . . . . . . . . . 42 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . 42 Erasable Programmable Read-Only Memory (EPROM) . . . . . 43 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2 Introduction
This section describes the organization of the memory on the MC68HC705JJ7/MC68HC705JP7.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Memory
Advance Information 35
Memory
2.3 Memory Map
The central processor unit (CPU) can address 8 kilobytes of memory space as shown in Figure 2-1. The memory map includes: * The erasable programmable read-only memory (EPROM) portion of memory holds the program instructions, fixed data, user-defined vectors, and interrupt service routines. The random-access memory (RAM) portion of memory holds variable data. Input/output (I/O) registers are memory mapped so that the CPU can access their locations in the same way that it accesses all other memory locations.
* *
$1EFF
Figure 2-1. Memory Map
2.4 Input/Output Registers
Figure 2-2 and Figure 2-3 summarize: * * The first 32 addresses of the memory space, $0000-$001F, containing the I/O registers section One I/O register located outside the 32-byte I/O section, which is the computer operating properly register (COPR) mapped at $1FF0
Advance Information 36 Memory
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Memory Input/Output Registers
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
Register Name Port A Data Register Port B Data Register Port C Data Register * Analog MUX Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register * Unused Core Timer Status & Control Register Core Timer Counter Serial Control Register Serial Status Register Serial Data Register IRQ Status & Control Register Personality EPROM Bit Select Register Personality EPROM Status & Control Register Port A and Port C Pulldown Register * Port B Pulldown Register Timer Control Register Timer Status Register Input Capture Register (MSB) Input Capture Register (LSB) Output Compare Register (MSB) Output Compare Register (LSB) Timer Counter Register (MSB) Timer Counter Register (LSB) Alternate Counter Register (MSB) Alternate Counter Register (LSB) EPROM Programming Register Analog Control Register Analog Status Register Reserved
* Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Figure 2-2. I/O Registers
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Memory
Advance Information 37
Memory
Addr. $0000
Register Read: Port A Data Register (PORTA) Write: See page 85. Reset: Read: Port B Data Register (PORTB) Write: See page 90. Reset: Read: Port C(1) Data Register (PORTC) Write: See page 102. Reset: Read: Analog Multiplex Register (AMUX) Write: See page 110. Reset: Read: Data Direction Register A (DDRA) Write: See page 86. Reset:
Bit 7 0
6 0
5 PA5
4 PA4
3 PA3
2 PA2
1 PA1
Bit 0 PA0
Unaffected by reset PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
$0001
Unaffected by reset PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
$0002
Unaffected by reset HOLD 1 0 DHOLD 0 0 INV 0 DDRA5 0 DDRB5 0 DDRC5 0 VREF 0 DDRA4 0 DDRB4 0 DDRC4 0 MUX4 0 DDRA3 0 DDRB3 0 DDRC3 0 MUX3 0 DDRA2 0 DDRB2 0 DDRC2 0 MUX2 0 DDRA1 0 DDRB1 0 DDRC1 0 MUX1 0 DDRA0 0 DDRB0 0 DDRC0 0
$0003
$0004
0
0 DDRB6 0 DDRC6 0
$0005
Read: Data Direction Register B DDRB7 (DDRB) Write: See page 91. Reset: 0 Read: Data Direction Register C DDRC7 (DDRC) Write: See page 103. Reset: 0 Unimplemented
$0006
$0007
$0008
Core Timer Status and Control Read: Register (CTSCR) Write: See page 153. Reset: Read: Core Timer Counter Register (CTCR) Write: See page 155. Reset:
CTOF
RTIF
CTOFE 0 5
RTIE 0 4
0 CTOFR 0 3
0 RTIFR 0 2
RT1 1 1
RT0 1 Bit 0
0 Bit 7
0 6
$0009
0
0
0
0 R
0 = Reserved
0
0 U = Unaffected
0
= Unimplemented 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Figure 2-3. Register Summary (Sheet 1 of 4)
Advance Information 38 Memory MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Memory Input/Output Registers
Addr. $000A
Register Read: SIOP Control Register (SCR) Write: See page 145. Reset: Read: SIOP Status Register (SSR) Write: See page 148. Reset: Read: SIOP Data Register (SDR) Write: See page 149. Reset:
Bit 7 SPIE 0 SPIF
6 SPE 0 DCOL
5 LSBF 0 0
4 MSTR 0 0
3 0 SPIR 0 0
2 CPHA 0 0
1 SPR1 0 0
Bit 0 SPR0 0 0
$000B
0 Bit 7
0 6
0 5
0 4
0 3
0 2
0 1
0 Bit 0
$000C
Read: $000D IRQ Status and Control Register (ISCR) Write: See page 58. Reset: $000E Read: PEPROM Bit Select Register (PEBSR) Write: See page 177. Reset:
IRQE 1 PEB7 0
OM2 1 PEB6 0 0
OM1 0 PEB5 0 PEPGM 0
0 R 0 PEB4 0 0
IRQF
0
0 IRQR
0
0 PEB3 0 0 R
0 PEB2 0 0 R 0
U PEB1 0 0 R 0
0 PEB0 0 PEPRZF
$000F
Read: PEDATA PEPROM Status and Control Register (PESCR) Write: See page 178. Reset: U Read: Pulldown Register Port A and Port C(1) (PDRA) Write: PDICH See page 87. Reset: 0 Read: Pulldown Register B (PDRB) Write: See page 92. Reset: Read: Timer Control Register (TCR) Write: See page 170. Reset:
0
0
0
1
$0010
PDICL 0
PDIA5 0
PDIA4 0
PDIA3 0
PDIA2 0
PDIA1 0
PDIA0 0
$0011
PDIB7 0 ICIE 0
PDIB6 0 OCIE 0
PDIB5 0 TOIE 0
PDIB4 0 0
PDIB3 0 0
PDIB2 0 0
PDIB1 0 IEDG U
PDIB0 0 OLVL 0
$0012
0 R
0 = Reserved
0
= Unimplemented 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
U = Unaffected
Figure 2-3. Register Summary (Sheet 2 of 4)
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Memory
Advance Information 39
Memory
Addr. $0013
Register Read: Timer Status Register (TSR) Write: See page 172. Reset: Read: Input Capture Register High (ICRH) Write: See page 166. Reset: Read: Input Capture Register Low (ICRL) Write: See page 166. Reset: Read: Output Compare Register High (OCRH) Write: See page 168. Reset: Read: Output Compare Register Low (OCRL) Write: See page 168. Reset: Read: Programmable Timer Register High (TMRH) Write: See page 163. Reset: Read: Programmable Timer Register Low (TMRL) Write: See page 163. Reset: Read: Alternate Counter Register High (ACRH) Write: See page 165. Reset: Read: Alternate Counter Register Low (ACRL) Write: See page 165. Reset:
Bit 7 ICF
6 OCF
5 TOF
4 0
3 0
2 0
1 0
Bit 0 0
U Bit 15
U 14
U 13
0 12
0 11
0 10
0 9
0 Bit 8
$0014
Unaffected by reset Bit 7 6 5 4 3 2 1 Bit 0
$0015
Unaffected by reset Bit 15 14 13 12 11 10 9 Bit 8
$0016
Unaffected by reset Bit 7 6 5 4 3 2 1 Bit 0
$0017
Unaffected by reset Bit 15 14 13 12 11 10 9 Bit 8
$0018
1 Bit 7
1 6
1 5
1 4
1 3
1 2
1 1
1 Bit 0
$0019
1 Bit 15
1 14
1 13
1 12
1 11
1 10
0 9
0 Bit 8
$001A
1 Bit 15
1 14
1 13
1 12
1 11
1 10
1 9
1 Bit 8
$001B
1
1
1
1 R
1 = Reserved
1
0 U = Unaffected
0
= Unimplemented 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Figure 2-3. Register Summary (Sheet 3 of 4)
Advance Information 40 Memory
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Memory Input/Output Registers
Addr. $001C
Register Read: EPROM Programming Register (EPROG) Write: See page 184. Reset: Read: Analog Counter Register (ACR) Write: See page 115. Reset: Read: Analog Status Register (ASR) Write: See page 115. Reset: Reserved
Bit 7 0
6 0 R
5 0 R 0 ATD1 0 0 CPFR2
4 0 R 0 ICEN 0 0 CPFR1 0 R
3 0 R 0 CPIE 0 COE1 0 R
2 ELAT 0 CP2EN 0 VOFF 0 R
1 MPGM 0 CP1EN 0 CMP2
Bit 0 EPGM 0 ISEN 0 CMP1 R
0 CHG 0 CPF2
0 ATD2 0 CPF1
$001D
$001E
0 R
0 R
0 R
0 R
0 R
$001F $1FEF
Reserved
R
R
R
R
R
R
R
R
$1FF0
Read: COP and Security Register (COPR) Write: EPMSEC See pages 43, 137, 156, and 188. Reset:
OPT Unaffected by reset = Unimplemented R = Reserved U = Unaffected
COPC
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Figure 2-3. Register Summary (Sheet 4 of 4)
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Memory
Advance Information 41
Memory
2.5 User and Interrupt Vector Mapping
The interrupt vectors are contained in the upper memory addresses above $1FF0 as shown in Figure 2-4.
Address $1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF Register Name COP Register and EPROM Security Mask Option Register Analog Interrupt Vector (MSB) Analog Interrupt Vector (LSB) Serial Interrupt Vector (MSB) Serial Interrupt Vector ((LSB) Timer Interrupt Vector (MSB) Timer Interrupt Vector (LSB) Core Timer Interrupt Vector (MSB) Core Timer Interrupt Vector (LSB) External IRQ Vector (MSB) External IRQ Vector (LSB) SWI Vector (MSB) SWI Vector (LSB) Reset Vector (MSB) Reset Vector (LSB)
Figure 2-4. Vector Mapping
2.6 Random-Access Memory (RAM)
The 224 addresses from $0020 to $00FF serve as both the user RAM and the stack RAM. The central processor unit (CPU) uses five RAM bytes to save all CPU register contents before processing an interrupt. During a subroutine call, the CPU uses two bytes to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
Advance Information 42 Memory
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Memory Erasable Programmable Read-Only Memory (EPROM)
2.7 Erasable Programmable Read-Only Memory (EPROM)
The EPROM is located in three areas of the memory map: * * Addresses $0700-$1EFF contain 6144 bytes of user EPROM. Addresses $1FF0-$1FF1 contain 2 bytes of EPROM reserved for user vectors and COP and security register (COPR), and the mask option register. Only bit 7 of $1FF0 is a programmable bit. Addresses $1FF2-$1FFF contain 14 bytes of interrupt vectors.
*
2.8 COP Register
As shown in Figure 2-5, a register location is provided at $1FF0 to set the EPROM security(1), select the optional features, and reset the COP watchdog timer. The OPT bit controls the function of the PB4 port pin and the availability to add an offset to any measured analog voltages. See 8.5 Analog Status Register for more information
Address: $1FF0 $1FF0 Read: OPT Write: EPMSEC Reset: = Unimplemented Unaffected by reset COPC Bit 7 6 5 4 3 2 1 Bit 0
Figure 2-5. COP and Security Register (COPR)
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users.
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Memory
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Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2 3.3 3.4 3.5 3.6 3.7 3.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.2 Introduction
This section describes the central processor unit (CPU) registers. Figure 3-1 shows the five CPU registers. CPU registers are not part of the memory map.
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Central Processor Unit (CPU)
7 A 7 X 15 0 15 1 1 1 0 0 0 0 0 10 PCH 7 1 1 5 1 4 H I N Z 0 0 8 1 7 PCL 0 C CONDITION CODE REGISTER (CCR) 6 1 5 SP 0 PROGRAM COUNTER (PC) 0 STACK POINTER (SP) 0 INDEX REGISTER (X) 0 ACCUMULATOR (A)
HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG
Figure 3-1. M68HC05 Programming Model
3.3 Accumulator
The accumulator is a general-purpose 8-bit register as shown in Figure 3-2. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 3-2. Accumulator (A)
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Central Processor Unit (CPU) Index Register
3.4 Index Register
The index register is a general-purpose 8-bit register as shown in Figure 3-3. In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand. The 8-bit index register can also serve as a temporary data storage location.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 3-3. Index Register (X)
3.5 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack as shown in Figure 3-4. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer initializes to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Bit 15 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 3-4. Stack Pointer (SP) The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations.
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Central Processor Unit (CPU)
3.6 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched as shown in Figure 3-5. The three most significant bits of the program counter are ignored internally and appear as 111 during stacking and subroutine calls. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
Bit 15 Read: 1 Write: Reset: 0 0 0 Loaded with vector from $1FFE and $1FFF 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 3-5. Program Counter (PC)
3.7 Condition Code Register
The condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111 as shown in Figure 3-6. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: 1 Write: Reset: 1 1 1 U 1 U U U 1 1 H I N C Z 6 5 4 3 2 1 Bit 0
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
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Central Processor Unit (CPU) Condition Code Register
Half-Carry Flag (H) The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary coded decimal (BCD) arithmetic operations. Reset has no effect on the half-carry flag. Interrupt Mask (I) Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is a logic 0, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. The CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After a reset, the interrupt mask is set and can be cleared only by a CLI instruction. Negative Flag (N) The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. Reset has no affect on the negative flag. Zero Flag (Z) The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. Reset has no affect on the zero flag. Carry/Borrow Flag (C) The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. Reset has no effect on the carry/borrow flag.
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Central Processor Unit (CPU)
3.8 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations.
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Section 4. Interrupts
4.1 Contents
4.2 4.3 4.4 4.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.6.1 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6.2 PA0-PA3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6.3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . 58 4.7 Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7.1 Core Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . 60 4.7.2 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8 Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 61 4.8.1 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.8.2 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.8.3 Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9 Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.10 Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.10.1 Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . .63 4.10.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2 Introduction
An interrupt temporarily stops normal program execution to process a particular event. An interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the
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central processor unit (CPU) registers on the stack and loads the program counter with a user-defined vector address.
4.3 Interrupt Vectors
Table 4-1 summarizes the reset and interrupt sources and vector assignments.
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit.
Table 4-1. Reset/Interrupt Vector Addresses
Function Source Power-on logic RESET pin Low-voltage reset Illegal address reset COP watchdog Software interrupt (SWI) User code IRQ/VPP pin External interrupt (IRQ) PA3 pin PA2 pin PA1 pin PA0 pin TOF bit RTIF bit ICF bit OCF bit TOF bit SPIF bit CPF1 bit CPF2 bit MOR Control Bit Global Hardware Mask Local Software Mask Priority (1 = Highest) Vector Address
-- -- COPEN(1) -- -- I bit IRQE bit 2 $1FFA-$1FFB -- -- Same priority as instruction $1FFC-$1FFD -- 1 $1FFE-$1FFF
Reset
PIRQ(2)
Core timer interrupts Programmable timer interrupts Serial interrupt Analog interrupt
--
I bit
TOFE bit RTIE bit ICIE bit OCIE bit TOIE bit SPIE bit CPIE bit
3
$1FF8-$1FF9
-- -- --
I bit I bit I bit
4 5 6
$1FF6-$1FF7 $1FF4-$1FF5 $1FF2-$1FF3
1. COPEN enables the COP watchdog timer. 2. PIRQ enables port A external interrupts on PA0-PA3.
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4.4 Interrupt Processing
To begin servicing an interrupt, the CPU does these actions: * * * Stores the CPU registers on the stack in the order shown in Figure 4-1 Sets the I bit in the condition code register to prevent further interrupts Loads the program counter with the contents of the appropriate interrupt vector locations as shown in Table 4-1
The return-from-interrupt (RTI) instruction causes the CPU to recover its register contents from the stack as shown in Figure 4-1. The sequence of events caused by an interrupt is shown in the flowchart in Figure 4-2.
$0020 $0021
Bottom of RAM
$00BE $00BF $00C0 $00C1 $00C2 Unstacking Order n n+1 n+2 n+3 n+4 Condition Code Register Accumulator Index Register Program Counter (High Byte) Program Counter (Low Byte) 5 4 3 2 1 $00FD $00FE $00FF Top of Stack (RAM) Stacking Order 1 2 3 4 5 Bottom of Stack
Figure 4-1. Interrupt Stacking Order
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FROM RESET
YES
I BIT SET? NO
EXTERNAL INTERRUPT? NO
YES
CLEAR IRQ LATCH
CORE TIMER INTERRUPT? NO TIMER INTERRUPT? NO SERIAL INTERRUPT? NO ANALOG INTERRUPT? NO
YES
YES
YES
YES
STACK PCL, PCH, X, A, CCR SET I BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO RTI INSTRUCTION? NO
YES
YES
UNSTACK CCR, A, X, PCH, PCL
EXECUTE INSTRUCTION
Figure 4-2. Interrupt Flowchart
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Interrupts Software Interrupt
4.5 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable interrupt.
4.6 External Interrupts
These sources can generate external interrupts: * * IRQ/VPP pin PA3-PA0 pins
Setting the I bit in the condition code register or clearing the IRQE bit in the interrupt status and control register disables these external interrupts.
4.6.1 IRQ/VPP Pin An interrupt signal on the IRQ/VPP pin latches an external interrupt request. To help clean up slow edges, the input from the IRQ/VPP pin is processed by a Schmitt trigger gate. When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQE bit in the IRQ status and control register (ISCR). If the I bit is clear and the IRQE bit is set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. Figure 4-3 shows the logic for external interrupts.
NOTE:
If the IRQ/VPP pin is not in use, it should be connected to the VDD pin. The IRQ/VPP pin can be negative edge-triggered only or negative edgeand low level-triggered. External interrupt sensitivity is programmed with the LEVEL bit in the mask option register (MOR).
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VPP TO USER EPROM AND PEPROM TO BIH & BIL INSTRUCTION PROCESSING
IRQ/VPP
PA3 VDD
PA2
IRQ LATCH R
EXTERNAL INTERRUPT REQUEST
PA1
PA0
RST IRQ VECTOR FETCH LEVEL IRQR PIRQ IRQE IRQF
MASK OPTION REGISTER ($1FF1) INTERNAL DATA BUS
IRQ STATUS/CONTROL REGISTER ($000D)
Figure 4-3. External Interrupt Logic With the edge- and level-sensitive trigger MOR option, a falling edge or a low level on the IRQ/VPP pin latches an external interrupt request. The edge- and level-sensitive trigger MOR option allows connection to the IRQ/VPP pin of multiple wired-OR interrupt sources. As long as any source is holding the IRQ low, an external interrupt request is present, and the CPU continues to execute the interrupt service routine. With the edge-sensitive-only trigger option, a falling edge on the IRQ/VPP pin latches an external interrupt request. A subsequent interrupt request can be latched only after the voltage level on the IRQ/VPP pin returns to a logic 1 and then falls again to logic 0.
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NOTE:
The response of the IRQ/VPP pin can be affected if the external interrupt capability of the PA0 through PA3 pins is enabled. If the port A pins are enabled as external interrupts, then any high level on a PA0-PA3 pin will cause the IRQ changes and state to be ignored until all of the PA0-PA3 pins have returned to a low level.
4.6.2 PA0-PA3 Pins Programming the PIRQ bit in the MOR to a logic 1 enables the PA0-PA3 pins (PA0:3) to serve as additional external interrupt sources. A rising edge on a PA0:3 pin latches an external interrupt request. After completing the current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQE bit in the ISCR. If the I bit is clear and the IRQE bit is set, the CPU then begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. The PA0:3 pins can be edge-triggered or edge- and level-triggered. External interrupt triggering sensitivity is selected by the LEVEL bit in the MOR. With the edge- and level-sensitive trigger MOR option, a rising edge or a high level on a PA0:3 pin latches an external interrupt request. The edge- and level-sensitive trigger MOR option allows connection to a PA0:3 pin of multiple wired-OR interrupt sources. As long as any source is holding the pin high, an external interrupt request is present, and the CPU continues to execute the interrupt service routine. With the edge-sensitive only trigger MOR option, a rising edge on a PA0:3 pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to a logic 0 and then rises again to a logic 1.
NOTE:
If the port A pins are enabled as external interrupts, then a high level on any PA0:3 pin will drive the state of the IRQ function such that the
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IRQ/VPP pin and other PA0:3 pins are to be ignored until ALL of the PA0:3 pins have returned to a low level. Similarly, if the IRQ/VPP pin is at a low level, the PA0:3 pins will be ignored until the IRQ/VPP pin returns to a high state.
4.6.3 IRQ Status and Control Register (ISCR) The IRQ status and control register (ISCR), shown in Figure 4-4, contains an external interrupt mask (IRQE), an external interrupt flag (IRQF), and a flag reset bit (IRQR). Unused bits will read as logic 0s. The ISCR also contains two control bits for the oscillators, external pin oscillator, and internal low-power oscillator. Reset sets the IRQE and OM2 bits and clears all the other bits.
Address: $000D Bit 7 Read: IRQE Write: Reset: 1 1 0 OM2 OM1 R 0 R 0 = Reserved 0 IRQR U U = Unaffected 0 6 5 4 0 3 IRQF 2 0 1 0 Bit 0 0
= Unimplemented
Figure 4-4. IRQ Status and Control Register (ISCR) IRQE -- External Interrupt Request Enable Bit This read/write bit enables external interrupts. Reset sets the IRQE bit. 1 = External interrupt processing enabled 0 = External interrupt processing disabled OM1 and OM2 -- Oscillator Select Bits These bits control the selection and enabling of the oscillator source for the MCU. One choice is the internal low-power oscillator (LPO). The other choice is the external pin oscillator (EPO) which is common to most M68HC05 MCU devices. The EPO uses external components
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like filter capacitors and a crystal or ceramic resonator and consumes more power. The selection and enable conditions for these two oscillators are shown in Table 4-2. Table 4-2. Oscillator Selection
Oscillator Selected by CPU Internal External Internal Internal Internal Low-Power Oscillator (LPO) Enabled Disabled Enabled Enabled External Pin Oscillator (EPO) Disabled Enabled Disabled Enabled Power Consumption Lowest Normal Lowest Normal
OM2
OM1
0 0 1 1
0 1 0 1
Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2 set is provided so that the EPO can be started and allowed to stabilize while the LPO still clocks the MCU. The reset state is for OM1 to be cleared and OM2 to be set, which selects the LPO and disables the EPO. IRQF -- External Interrupt Request Flag The IRQ flag is a clearable, read-only bit that is set when an external interrupt request is pending. Writing to the IRQF bit has no effect. Reset clears the IRQF bit. 1 = Interrupt request pending 0 = No interrupt request pending The following conditions set the IRQ flag: * An external interrupt signal on the IRQ/VPP pin * An external interrupt signal on pin PA0, PA1, PA2, or PA3 when the PA0-PA3 pins are enabled by the PIRQ bit in the MOR to serve as external interrupt sources. The following conditions clear the IRQ flag: * When the CPU fetches the interrupt vector * When a logic 1 is written to the IRQR bit
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IRQR -- Interrupt Request Reset Bit This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Writing a logic 1 to IRQR clears the IRQF. Writing a logic 0 to IRQR has no effect. IRQR always reads as a logic 0. Reset has no effect on IRQR. 1 = Clear IRQF flag bit 0 = No effect
4.7 Core Timer Interrupts
The core timer can generate the following interrupts: * * Timer overflow interrupt Real-time interrupt
Setting the I bit in the condition code register disables core timer interrupts. The controls and flags for these interrupts are in the core timer status and control register (CTSCR) located at $0008.
4.7.1 Core Timer Overflow Interrupt An overflow interrupt request occurs if the core timer overflow flag (TOF) becomes set while the core timer overflow interrupt enable bit (TOFE) is also set. The TOF flag bit can be reset by writing a logic 1 to the CTOFR bit in the CTSCR or by a reset of the device.
4.7.2 Real-Time Interrupt A real-time interrupt request occurs if the real-time interrupt flag (RTIF) in the CTSCR becomes set while the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can be reset by writing a logical 1 to the RTIFR bit in the CTSCR or by a reset of the device.
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4.8 Programmable Timer Interrupts
The 16-bit programmable timer can generate an interrupt whenever the following events occur: * * * Input capture Output compare Timer counter overflow
Setting the I bit in the condition code register disables timer interrupts. The controls for these interrupts are in the timer control register (TCR) located at $0012 and in the status bits in the timer status register (TSR) located at $0013.
4.8.1 Input Capture Interrupt An input capture interrupt occurs if the input capture flag (ICF) becomes set while the input capture interrupt enable bit (ICIE) is also set. The ICF flag bit is in the TSR, and the ICIE enable bit is located in the TCR. The ICF flag bit is cleared by a read of the TSR with the ICF flag bit set, and then followed by a read of the LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected by reset.
4.8.2 Output Compare Interrupt An output compare interrupt occurs if the output compare flag (OCF) becomes set while the output compare interrupt enable bit (OCIE) is also set. The OCF flag bit is in the TSR and the OCIE enable bit is in the TCR. The OCF flag bit is cleared by a read of the TSR with the OCF flag bit set, and then followed by an access to the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is unaffected by reset.
4.8.3 Timer Overflow Interrupt A timer overflow interrupt occurs if the timer overflow flag (TOF) becomes set while the timer overflow interrupt enable bit (TOIE) is also set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR.
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The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set, and then followed by an access to the LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected by reset.
4.9 Serial Interrupts
The simple serial interface can generate the following interrupts: * * Receive sequence complete Transmit sequence complete
Setting the I bit in the condition code register disables serial interrupts. The controls for these interrupts are in the serial control register (SCR) located at $000A and in the status bits in the serial status register (SSR) located at $000B. A transfer complete interrupt occurs if the serial interrupt flag (SPIF) becomes set while the serial interrupt enable bit (SPIE) is also set. The SPIF flag bit is in the serial status register (SSR) located at $000B, and the SPIE enable bit is located in the serial control register (SCR) located at $000A. The SPIF flag bit is cleared by a read of the SSR with the SPIF flag bit set, and then followed by a read or write to the serial data register (SDR) located at $000C. The SPIF flag bit can also be reset by writing a one to the SPIR bit in the SCR.
4.10 Analog Interrupts
The analog subsystem can generate the following interrupts: * * * Voltage on positive input of comparator 1 is greater than the voltage on the negative input of comparator 1. Voltage on positive input of comparator 2 is greater than the voltage on the negative input of comparator 2. Trigger of the input capture interrupt from the programmable timer as described in 4.8.1 Input Capture Interrupt
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Setting the I bit in the condition code register disables analog subsystem interrupts. The controls for these interrupts are in the analog subsystem control register (ACR) located at $001D, and the status bits are in the analog subsystem status register (ASR) located at $001E.
4.10.1 Comparator Input Match Interrupt A comparator input match interrupt occurs if either compare flag bit (CPF1 or CPF2) in the ASR becomes set while the comparator interrupt enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits in the ASR. Reset clears these bits.
4.10.2 Input Capture Interrupt The analog subsystem can also generate an input capture interrupt through the 16-bit programmable timer. The input capture can be triggered when there is a match in the input conditions for the voltage comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the input capture enable (ICEN) in the ACR is set, then an input capture will be performed by the programmable timer. If the ICIE enable bit in the TCR is also set, then an input compare interrupt will occur. Reset clears these bits.
NOTE:
For the analog subsystem to generate an interrupt using the input capture function of the programmable timer, the ICEN enable bit in the ACR, and the ICIE and IEDG bits in the TCR must all be set.
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Section 5. Resets
5.1 Contents
5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . 68 5.5.3 Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 5.6 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.2 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.3 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.4 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.6.5 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6.7 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6.8 External Oscillator and Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .73
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Resets
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Resets
5.2 Introduction
This section describes the five reset sources and how they initialize the microcontroller unit (MCU). A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. These conditions produce a reset: * * * * * Initial power-up of device (power-on reset) A logic 0 applied to the RESET pin (external reset) Timeout of the computer operating properly (COP) watchdog (COP reset) Low voltage applied to the device (LVR reset) Fetch of an opcode from an address not in the memory map (illegal address reset)
Figure 5-1 shows a block diagram of the reset sources and their interaction.
MASK OPTION REGISTER ($1FF1) LVREN COPEN
INTERNAL DATA BUS
COP WATCHDOG LOW-VOLTAGE RESET VDD POWER-ON RESET ILLEGAL ADDRESS RESET INTERNAL ADDRESS BUS RESET S D RESET LATCH R 3-CYCLE CLOCKED 1-SHOT INTERNAL CLOCK RST TO CPU AND SUBSYSTEMS
Figure 5-1. Reset Sources
Advance Information 66 Resets MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Resets Power-On Reset
5.3 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. A delay of 16 or 4064 internal bus cycles (tcyc) after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at logic 0 at the end of this multiple tcyc time, the MCU remains in the reset condition until the signal on the RESET pin goes to a logic 1.
5.4 External Reset
A logic 0 applied to the RESET pin for a minimum of one and one half tcyc generates an external reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the internal RST signal that resets the CPU and peripherals. The RESET pin can also be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. This reset pulldown device will only be asserted for three to four cycles of the internal bus or as long as the internal reset source is asserted.
NOTE:
Do not connect the RESET pin directly to VDD, as this may overload some power supply designs if the internal pulldown on the RESET pin should activate. If an external reset function is not required, the RESET pin should be left unconnected.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Resets
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Resets
5.5 Internal Resets
The four internally generated resets are: * * * * Initial power-on reset (POR) function COP watchdog timer reset Low-voltage reset (LVR) Illegal address detector
Only the COP watchdog timer reset, low-voltage reset, and illegal address detector will also assert the pulldown device on the RESET pin for the duration of the reset function or for three to four internal bus cycles, whichever is longer. 5.5.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out); that function can be performed by the LVR. Depending on the DELAY bit in the mask option register (MOR), there is an oscillator stabilization delay of 16 or 4064 internal bus cycles after the LPO becomes active. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 16- or 4064-cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will not activate the pulldown device on the RESET pin. VDD must drop below VPOR for the internal POR circuit to detect the next rise of VDD. 5.5.2 Computer Operating Properly (COP) Reset A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic 0 to the COPC bit of the COPR register at location $1FF0. The COPC bit, shown in Figure 5-2, is a write-only bit.
Advance Information 68 Resets MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Resets Internal Resets
Address:
$1FF0 Bit 7 6 OPT U U U U = Unaffected U U U 5 4 3 2 1 Bit 0
Read: Write: Reset:
EPMSEC U
COPC U
= Unimplemented
Figure 5-2. COP and Security Register (COPR) EPMSEC -- EPROM Security(1) Bit The EPMSEC bit is an EPROM, write-only security bit to protect the contents of the user EPROM code stored in locations $0700-$1FFF. OPT -- Optional Features Bit The OPT bit enables two additional features: direct drive by comparator 1 output to PB4 and voltage offset capability to sample capacitor in analog subsystem. 1 = Optional features enabled 0 = Optional features disabled
NOTE:
See 8.8.1 Voltage Comparator 1 and 8.11 Sample and Hold for further descriptions of the OPT bit. COPC -- COP Clear Bit COPC is a write-only bit. Periodically writing a logic 0 to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 1 = No effect on COP watchdog timer 0 = Reset COP watchdog timer The COP watchdog reset will assert the pulldown device to pull the RESET pin low for three to four cycles of the internal bus. The COP watchdog reset function can be enabled or disabled by programming the COPEN bit in the MOR.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users.
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Resets
5.5.3 Low-Voltage Reset (LVR) The LVR activates the RST reset signal to reset the device when the voltage on the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low for three to four cycles of the internal bus. The LVR reset function can be enabled or disabled by programming the LVREN bit in the MOR.
NOTE:
The LVR is intended for applications where the VDD supply voltage normally operates above 4.5 volts.
5.5.4 Illegal Address Reset An opcode fetch (execution of an instruction) at an address that is not in the EPROM (locations $0700-$1FFF) or the RAM (locations $0020-$00FF) generates an illegal address reset. The illegal address reset will assert the pulldown device to pull the RESET pin low for three to four cycles of the internal bus.
5.6 Reset States
This subsection describe how the various resets initialize the MCU.
5.6.1 CPU A reset has these effects on the CPU: * * * * * Loads the stack pointer with $FF Sets the I bit in the condition code register, inhibiting interrupts Loads the program counter with the user-defined reset vector from locations $1FFE and $1FFF Clears the stop latch, enabling the CPU clock Clears the wait latch, bringing the CPU out of the wait mode
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MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Resets Reset States
5.6.2 I/O Registers A reset has these effects on input/output (I/O) registers: * Clears bits in data direction registers configuring pins as inputs: - DDRA5-DDRA0 in DDRA for port A - DDRB7-DDRB0 in DDRB for port B - DDRC7-DDRC0 in DDRC for port C(1) * Clears bits in pulldown inhibit registers to enable pulldown devices: - PDIA5-PDIA0 in PDRA for port A - PDIB7-PDIB0 in PDRB for port B - PDICH and PDICL in PDRA for port C(1) * * Has no effect on port A, B, or C(1) data registers Sets the IRQE bit in the interrupt status and control register (ISCR)
5.6.3 Core Timer A reset has these effects on the core timer: * * * Clears the core timer counter register (CTCR) Clears the core timer interrupt flag and enable bits in the core timer status and control register (CTSCR) Sets the real-time interrupt (RTI) rate selection bits (RT0 and RT1) such that the device will start with the longest real-time interrupt and longest COP timeout delays
5.6.4 COP Watchdog A reset clears the COP watchdog timeout counter.
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices
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5.6.5 16-Bit Programmable Timer A reset has these effects on the 16-bit programmable timer: * * * * * * * Initializes the timer counter registers (TMRH and TMRL) to a value of $FFFC Initializes the alternate timer counter registers (ACRH and ACRL) to a value of $FFFC Clears all the interrupt enables and the output level bit (OLVL) in the timer control register (TCR) Does not affect the input capture edge bit (IEDG) in the TCR Does not affect the interrupt flags in the timer status register (TSR) Does not affect the input capture registers (ICRH and ICRL) Does not affect the output compare registers (OCRH and OCRL)
5.6.6 Serial Interface A reset has these effects on the serial interface: * * * Clears all bits in the SIOP control register (SCR) Clears all bits in the SIOP status register (SSR) Does not affect the contents of the SIOP data register (SDR)
A reset, therefore, disables the SIOP and leaves the shared port B pins as general I/O. Any pending interrupt flag is cleared and the SIOP interrupt is disabled. Also the baud rate defaults to the slowest rate.
5.6.7 Analog Subsystem A reset has these effects on the analog subsystem: * * * Clears all the bits in the multiplex register (AMUX) bits except the hold switch bit (HOLD) which is set Clears all the bits in the analog control register (ACR) Clears all the bits in the analog status register (ASR)
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MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Resets Reset States
A reset, therefore, connects the negative input of comparator 2 to the channel selection bus, which is switched to VSS. Both comparators are set up as non-inverting (a higher positive voltage on the positive input results in a positive output) and both are powered down. The current source and discharge device on the PB0/AN0 pin is disabled and powered down. Any analog subsystem interrupt flags are cleared and the analog interrupt is disabled. Direct drive by comparator 1 to the PB4 pin and the voltage offset to the sample capacitor are disabled (if both are enabled by the OPT bit being set in the COPR).
5.6.8 External Oscillator and Internal Low-Power Oscillator A reset presets the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR) such that the device runs from the internal oscillator (OM1 = 0, OM2 = 1) which has these effects on the oscillators: * * * The internal low-power oscillator is enabled and selected. The external oscillator is disabled. The CPU bus clock is driven from the internal low-power oscillator.
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Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 6. Operating Modes
6.1 Contents
6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.4 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.2 Introduction
This section describes the operation of the device with respect to the oscillator source and the low-power modes: * * * * Stop mode Wait mode Halt mode Data-retention mode
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Operating Modes
6.3 Oscillator Source
The microcontroller unit (MCU) can be clocked by either an internal low-power oscillator (LPO) without external components or by an external pin oscillator (EPO) which uses external components. The enable and selection of the clock source is determined by the state of the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR) as shown in Figure 6-1.
Address: $000D Bit 7 Read: Write: Reset: IRQE 1 6 OM2 1 5 OM1 0 4 0 R 0 0 R 0 = Reserved 3 IRQF 2 0 1 0 IRQR 0 0 Bit 0 0
= Unimplemented
Figure 6-1. IRQ Status and Control Register (ISCR) IRQE -- External Interrupt Request Enable Bit This read/write bit enables external interrupts. Refer to Section 4. Interrupts for more details. OM1 and OM2 -- Oscillator Select Bits These bits control the selection and enabling of the oscillator source for the MCU. One choice is the internal LPO and the other oscillator is the EPO which is common to most M68HC05 MCU devices. The EPO uses external components like filter capacitors and a crystal or ceramic resonator and consumes more power than the LPO. The selection and enable conditions for these two oscillators are shown in Table 6-1. Reset clears OM1 and sets OM2, which selects the LPO and disables the EPO. Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2 set is provided so that the EPO can be started up and allowed to stabilize while the LPO still clocks the MCU.
Advance Information 76 Operating Modes
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Operating Modes Low-Power Modes
Table 6-1. Oscillator Selection
Oscillator Selected Internal External Internal Internal Internal Low-Power Oscillator (LPO) Enabled Disabled Enabled Enabled External Pin Oscillator (EPO) Disabled Enabled Disabled Enabled Power Consumption Lowest Normal Lowest Normal
.
OM2
OM1
0 0 1 1
0 1 0 1
NOTE:
When switching from LPO to EPO, the user must be careful to ensure that the EPO has been enabled and powered up long enough to stabilize before shifting clock sources. IRQF -- External Interrupt Request Flag The IRQF flag is a clearable, read-only bit that is set when an external interrupt request is pending. Refer to Section 4. Interrupts for more details. IRQR -- Interrupt Request Reset Bit This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Refer to Section 4. Interrupts for more details.
6.4 Low-Power Modes
Four modes of operation reduce power consumption: * * * * Stop mode Wait mode Halt mode Data-retention mode
Figure 6-2 shows the sequence of events in stop, wait, and halt modes.
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Operating Modes
STOP
HALT
WAIT
SWAIT BIT IN MOR SET? NO
YES
CLEAR I BIT IN CCR. SET IRQE BIT IN ISCR. TURN OFF CPU CLOCK. KEEP OTHER MODULE CLOCKS ACTIVE.
CLEAR I BIT IN CCR. SET IRQE BIT IN ISCR. TURN OFF CPU CLOCK. KEEP OTHER MODULE CLOCKS ACTIVE.
CLEAR I BIT IN CCR. SET IRQE BIT IN ISCR. CLEAR CTOF, RTIF, CTOFE, AND RTIE BITS IN TSCR. CLEAR ICF, OCF, AND TOF BITS IN TSR. CLEAR ICIE, OCIE, AND TOIE BITS IN TCR. DISABLE EXTERNAL PIN OSCILLATOR. TURN OFF INTERNAL LOW-POWER OSCILLATOR.
YES
EXTERNAL RESET? NO
YES
EXTERNAL RESET? NO
EXTERNAL RESET? NO
YES
YES
EXTERNAL INTERRUPT? NO
YES
EXTERNAL INTERRUPT? NO
EXTERNAL INTERRUPT? NO
YES
YES
CORE TIMER INTERRUPT? NO
YES
CORE TIMER INTERRUPT? NO
YES
PROG. TIMER INTERRUPT? NO
YES
PROG. TIMER INTERRUPT? NO
TURN ON SELECTED OSCILLATOR. RESET STABILIZATION DELAY TIMER. YES
SIOP INTERRUPT? NO
YES
SIOP INTERRUPT? NO
YES
END OF STABILIZATION DELAY? NO
YES
ANALOG INTERRUPT? NO
YES
ANALOG INTERRUPT? NO
YES TURN ON CPU CLOCK.
COP RESET? NO
YES
COP RESET? NO
1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT. a. SAVE CPU REGISTERS ON STACK. b. SET I BIT IN CCR. c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-2. Stop/Wait/Halt Flowchart
Advance Information 78 Operating Modes MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Operating Modes Low-Power Modes
6.4.1 Stop Mode The STOP instruction puts the MCU in a mode with the lowest power consumption and affects the MCU as follows: * Turns off the central processor unit (CPU) clock and all internal clocks by stopping both the external pin oscillator and the internal low-power oscillator. The selection of the oscillator by the OM1 and OM2 bits in the ISCR is not affected. The stopped clocks turn off the COP watchdog, the core timer, the programmable timer, the analog subsystem, and the SIOP. Removes any pending core timer interrupts by clearing the core timer interrupt flags (CTOF and RTIF) in the core timer status and control register (CTSCR) Disables any further core timer interrupts by clearing the core timer interrupt enable bits (CTOFE and RTIE) in the CTSCR Removes any pending programmable timer interrupts by clearing the timer interrupt flags (ICF, OCF, and TOF) in the timer status register (TSR) Disables any further programmable timer interrupts by clearing the timer interrupt enable bits (ICIE, OCIE, and TOIE) in the timer control register (TCR) Enables external interrupts via the IRQ/VPP pin by setting the IRQE bit in the IRQ status and control register (ISCR). External interrupts are also enabled via the PA0 through PA3 pins, if the port A interrupts are enabled by the PIRQ bit in the mask option register (MOR). Enables interrupts in general by clearing the I bit in the condition code register
*
* *
*
*
*
The STOP instruction does not affect any other bits, registers, or I/O lines.
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Operating Modes
The following conditions bring the MCU out of stop mode: * An external interrupt signal on the IRQ/VPP pin -- A high-to-low transition on the IRQ/VPP pin loads the program counter with the contents of locations $1FFA and $1FFB. An external interrupt signal on a port A external interrupt pin -- If selected by the PIRQ bit in the MOR, a low-to-high transition on a PA3-PA0 pin loads the program counter with the contents of locations $1FFA and $1FFB. External reset -- A logic 0 on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF.
*
*
When the MCU exits stop mode, processing resumes after a stabilization delay of 16 or 4064 internal bus cycles, depending on the state of the DELAY bit in the MOR.
NOTE:
Execution of the STOP instruction without setting the SWAIT bit in the MOR will cause the oscillators to stop, and, therefore, disable the COP watchdog timer. If the COP watchdog timer is to be used, stop mode should be changed to halt mode as described in 6.4.3 Halt Mode.
6.4.2 Wait Mode The WAIT instruction puts the MCU in a low-power wait mode which consumes more power than the stop mode and affects the MCU as follows: * * * Enables interrupts by clearing the I bit in the condition code register Enables external interrupts by setting the IRQE bit in the IRQ status and control register Stops the CPU clock which drives the address and data buses, but allows the selected oscillator to continue to clock the core timer, programmable timer, analog subsystem, and SIOP
The WAIT instruction does not affect any other bits, registers, or I/O lines.
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MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Operating Modes Low-Power Modes
These conditions restart the CPU bus clock and bring the MCU out of wait mode: * An external interrupt signal on the IRQ/VPP pin -- A high-to-low transition on the IRQ/VPP pin loads the program counter with the contents of locations $1FFA and $1FFB. An external interrupt signal on a port A external interrupt pin -- If selected by PIRQ bit in the MOR, a low-to-high transition on a PA3-PA0 pin loads the program counter with the contents of locations $1FFA and $1FFB. A core timer interrupt -- A core timer overflow or a real-time interrupt loads the program counter with the contents of locations $1FF8 and $1FF9. A programmable timer interrupt -- A programmable timer interrupt driven by an input capture, output compare, or timer overflow loads the program counter with the contents of locations $1FF6 and $1FF7. An SIOP interrupt -- An SIOP interrupt driven by the completion of transmitted or received 8-bit data loads the program counter with the contents of locations $1FF4 and $1FF5. An analog subsystem interrupt -- An analog subsystem interrupt driven by a voltage comparison loads the program counter with the contents of locations $1FF2 and $1FF3. A COP watchdog reset -- A timeout of the COP watchdog resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF. Software can enable real-time interrupts so that the MCU can periodically exit the wait mode to reset the COP watchdog. An external reset -- A logic 0 on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF.
*
*
*
*
*
*
*
When the MCU exits the wait mode, there is no delay before code executes like occurs when exiting the stop or halt modes.
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6.4.3 Halt Mode The STOP instruction puts the MCU in halt mode if selected by the SWAIT bit in the MOR. Halt mode is identical to wait mode, except that a variable recovery delay occurs when the MCU exits halt mode. A recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can be selected by the DELAY bit in the MOR. If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP watchdog cannot be turned off inadvertently by a STOP instruction.
6.4.4 Data-Retention Mode In the data-retention mode, the MCU retains random-access memory (RAM) contents and CPU register contents at VDD voltages as low as 2.0 Vdc. The data retention feature allows the MCU to remain in a low-power consumption state during which it retains data, but the CPU cannot execute instructions. Current consumption in this mode is not tested. To put the MCU in the data retention mode: 1. Drive the RESET pin to a logic 0. 2. Lower the VDD voltage. The RESET pin must remain low continuously during data retention mode. To take the MCU out of the data retention mode: 1. Return VDD to normal operating voltage. 2. Return the RESET pin to a logic 1.
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Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 7. Parallel Input/Output
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.3 Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.4 Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3.5 Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.3 Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.4 Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.5 PB0, PBI, PB2, and PB3 Logic. . . . . . . . . . . . . . . . . . . . . . .93 7.4.6 PB4/AN4/TCMP/CMP1 Logic. . . . . . . . . . . . . . . . . . . . . . . . 94 7.4.7 PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.4.8 PB6/SDI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4.9 PB7/SCK Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.5 Port C (28-Pin Versions Only) . . . . . . . . . . . . . . . . . . . . . . . . 101 7.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.5.3 Port C Pulldown Devices . . . . . . . . . . . . . . . . . . . . . . . . . .103 7.5.4 Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6 Port Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
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Parallel Input/Output
7.2 Introduction
The MC68HC705JJ7 has 14 bidirectional input/output (I/O) pins which form two parallel I/O ports, A and B. The MC68HC705JP7 has 22 bidirectional I/O pins which form three parallel I/O ports, A, B and C. Each I/O pin is programmable as an input or an output. The contents of the data direction registers determine the data direction of each of the I/O pins. All I/O pins have software programmable pulldown devices which can be enabled or disabled globally by the SWPDI bit in the mask option register (MOR).
7.3 Port A
Port A is a 6-bit, general-purpose, bidirectional I/O port with these features: * * * * Individual programmable pulldown devices High current sinking capability on all port A pins, with a maximum total for port A High current sourcing capability on all port A pins, with a maximum total for port A External interrupt capability (pins PA3-PA0)
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Parallel Input/Output Port A
7.3.1 Port A Data Register The port A data register (PORTA) contains a bit for each of the port A pins. When a port A pin is programmed to be an output, the state of its data register bit determines the state of the output pin. When a port A pin is programmed to be an input, reading the port A data register returns the logic state of the pin. The upper two bits of the port A data register will always read as logic 0s.
Address: $0000 Bit 7 Read: Write: Reset: Alternate: = Unimplemented Unaffected by reset KYBD3 KYBD2 KYBD1 KYBD0 0 6 0 PA5 PA4 PA3 PA2 PA1 PA0 5 4 3 2 1 Bit 0
Figure 7-1. Port A Data Register (PORTA) PA5-PA0 -- Port A Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data.
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7.3.2 Data Direction Register A The contents of the port A data direction register (DDRA) determine whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the associated port A pin. A DDRA bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRA bit disables the output buffer for the associated port A pin. The upper two bits always read as logic 0s. A reset initializes all DDRA bits to logic 0s, configuring all port A pins as inputs and disabling the voltage comparators from driving PA4 or PA5.
Address: $0004 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 5 4 3 2 1 Bit 0
= Unimplemented
Figure 7-2. Data Direction Register A (DDRA) DDRA5-DDRA0 -- Port A Data Direction Bits These read/write bits control port A data direction. Reset clears the DDRA5-DDRA0 bits. 1 = Corresponding port A pin configured as output and pulldown device disabled 0 = Corresponding port A pin configured as input
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Parallel Input/Output Port A
7.3.3 Pulldown Register A All port A pins can have software programmable pulldown devices enabled or disabled globally by SWPDI bit in the MOR. These pulldown devices are controlled by the write-only pulldown register A (PDRA) shown in Figure 7-3. Clearing the PDIA5-PDIA0 bits in the PDRA turns on the pulldown devices if the port A pin is an input. Reading the PDRA returns undefined results since it is a write-only register; therefore, do not change the value in PDRA with read/modify/write instructions. On the MC68HC705JP7 the PDRA contains two pulldown control bits (PDICH and PDICL) for port C. Reset clears the PDIA5-PDIA0, PDICH, and PDICL bits, which turns on all the port A and port C pulldown devices.
Address: $0010 Bit 7 Read: Write: Reset: PDICH 0 PDICL 0 PDIA5 0 PDIA4 0 PDIA3 0 PDIA2 0 PDIA1 0 PDIA0 0 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA) PDICH -- Upper Port C Pulldown Inhibit Bits (MC68HC705JP7) Writing to this write-only bit controls the port C pulldown devices on the upper four bits (PC4-PC7). Reading these pulldown register A bits returns undefined data. Reset clears bit PDICH. 1 = Upper four port C pins pulldown devices turned off 0 = Upper four port C pins pulldown devices turned on if pin has been programmed by the DDRC to be an input PDICL -- Lower Port C Pulldown Inhibit Bits (MC68HC705JP7) Writing to this write-only bit controls the port C pulldown devices on the lower four bits (PC0-PC3). Reading these pulldown register A bits returns undefined data. Reset clears bit PDICL. 1 = Lower four port C pins pulldown devices turned off
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0 = Lower four port C pins pulldown devices turned on if pin has been programmed by the DDRC to be an input PDIA5-PDIA0 -- Port A Pulldown Inhibit Bits Writing to these write-only bits controls the port A pulldown devices. Reading these pulldown register A bits returns undefined data. Reset clears bits PDIA5-PDIA0. 1 = Corresponding port A pin pulldown device turned off 0 = Corresponding port A pin pulldown device turned on if pin has been programmed by the DDRA to be an input
7.3.4 Port A External Interrupts The PIRQ bit in the MOR enables the PA3-PA0 pins to serve as external interrupt pins in addition to the IRQ/VPP pin. The active interrupt state for the PA3-PA0 pins is a logic 1 or a rising edge. A state of the PIRQ bit in the MOR determines whether external interrupt inputs are edge-sensitive only or both edge- and level-sensitive. Port A interrupts are also interactive with each other and the IRQ/VPP pin as described in 4.6 External Interrupts.
NOTE:
When testing for external interrupts, the BIH and BIL instructions test the voltage on the IRQ/VPP pin, not the state of the internal IRQ signal. Therefore, BIH and BIL cannot test the port A external interrupt pins.
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Parallel Input/Output Port A
7.3.5 Port A Logic When a PA0:PA5 pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. When a PA0:PA5 pin is programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDR bit. Figure 7-4 shows the I/O logic of PA0-PA5 pins of port A. The data latch can always be written, regardless of the state of its DDR bits. Table 7-1 summarizes the operations of the port A pins.
EXTERNAL INTERRUPT REQUEST (PA0:3)
READ $0004 WRITE $0004 DATA DIRECTION REGISTER A BIT DDRAx
R INTERNAL DATA BUS
WRITE $0000
PORT A DATA REGISTER BIT PAx
PAx HIGH SINK/SOURCE CURRENT CAPABILITY
READ $0000 WRITE $0010 PULLDOWN REGISTER A BIT PDIAx
R RESET
SWPDI
PULLDOWN DEVICE
MASK OPTION REG. ($1FF1)
Figure 7-4. Port A I/O Circuit Table 7-1. Port A Pin Functions
Port A Pin(s) PA0 PA1 PA2 PA3 PA4 PA5 SWPDI (in MOR) 0 0 1 X(2) Port A PDIAx 0 1 X X(2) DDRAx(1) 0 0 0 1 PORTA Access (Pin or Data Register) Read Pin Pin Pin Data Write Data Data Data Data Result on Port A Pins Pulldown On Off Off Off Pin PAx in PAx in PAx in PAx out
1. DDRA can always be read or written. 2. Don't care
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7.4 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port with these features: * * * * * * * Programmable pulldown devices PB0-PB4 are shared with the analog subsystem. PB3 and PB4 are shared with the 16-bit programmable timer. PB4 can be driven directly by the output of comparator 1. PB5-PB7 are shared with the simple serial interface (SIOP). High current sinking capability on the PB4 pin High current sourcing capability on the PB4 pin
7.4.1 Port B Data Register The port B data register (PORTB) contains a bit for each of the port B pins. When a port B pin is programmed to be an output, the state of its data register bit determines the state of the output pin. When a port B pin is programmed to be an input, reading the port B data register returns the logic state of the pin. Reset has no effect on port B data.
Address: $0001 Bit 7 Read: Write: Reset: Alternate: Alternate: Alternate: SCK SCK SCK SDI SDI SDI SDO SDO SDO PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 Bit 0 PB0
Unaffected by reset AN4 TCMP CMP1 AN3 TCAP TCAP AN2 AN2 AN2 AN1 AN1 AN1 AN0 AN0 AN0
Figure 7-5. Port B Data Register (PORTB) PB0-PB7 -- Port B Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data.
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Parallel Input/Output Port B
7.4.2 Data Direction Register B The contents of the port B data direction register (DDRB) determine whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the associated port B pin. A DDRB bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRB bit disables the output buffer for the associated port B pin. A reset initializes all DDRB bits to logic 0s, configuring all port B pins as inputs.
Address: $0005 Bit 7 Read: DDRB7 Write: Reset: 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 6 5 4 3 2 1 Bit 0
Figure 7-6. Data Direction Register B (DDRB) DDRB7-DDRB0 -- Port B Data Direction Bits These read/write bits control port B data direction. Reset clears the bits DDRB7-DDRB0. 1 = Corresponding port B pin configured as output and pulldown device disabled 0 = Corresponding port B pin configured as input
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7.4.3 Pulldown Register B All port B pins can have software programmable pulldown devices enabled or disabled globally by the SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown register B (PDRB) shown in Figure 7-7. Clearing the PDIB7-PDIB0 bits in the PDRB turns on the pulldown devices if the port B pin is an input. Reading the PDRB returns undefined results since it is a write-only register. Reset clears the PDIB7-PDIB0 bits, which turns on all the port B pulldown devices.
Address: $0011 Bit 7 Read: Write: Reset: PDIB7 0 PDIB6 0 PDIB5 0 PDIB4 0 PDIB3 0 PDIB2 0 PDIB1 0 DIB0 0 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB) PDIB7-PDIB0 -- Port B Pulldown Inhibit Bits Writing to these write-only bits controls the port B pulldown devices. Reading these pulldown register B bits returns undefined data. Reset clears bits PDIB7-PDIB0. 1 = Corresponding port B pin pulldown device turned off 0 = Corresponding port B pin pulldown device turned on if pin has been programmed by the DDRB to be an input
7.4.4 Port B Logic All port B pins have the general I/O port logic similar to port A; but they also share this function with inputs or outputs from other modules, which are also attached to the pin itself or override the general I/O function. PB0, PB1, PB2, and PB3 simply share their inputs with another module. PB4, PB5, PB6, and PB7 will have their operation altered by outputs or controls from other modules.
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Parallel Input/Output Port B
7.4.5 PB0, PBI, PB2, and PB3 Logic The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and PB3 pins of port B. When these port B pins are programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. When these port B pins are programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDRB bit. The operations of the PB0-PB3 pins are summarized in Table 7-2.
READ $0005 WRITE $0005 R DATA DIRECTION REGISTER B BIT DDRBx
ANALOG SUBSYSTEM, AND PROGRAMMABLE TIMER INPUT CAPTURE (PINS PB0, PB1, PB2, PB3)
WRITE $0001 INTERNAL DATA BUS
PORT BDATA REGISTER BIT PBx
PBx
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIBx PULLDOWN DEVICE
R RESET
SWPDI MASK OPTION REG. ($1FF1)
Figure 7-8. PB0-PB3 Pin I/O Circuit The PB0-PB3 pins share their inputs with another module. When using the other attached module, these conditions must be observed: 1. If the DDRB configures the pin as an output, then the port data register can provide an output which may conflict with any external input source to the other module. The pulldown device will be disabled in this case. 2. If the DDRB configures the pin as an input, then reading the port data register will return the state of the input in terms of the digital threshold for that pin (analog inputs will default to logic states). 3. If DDRB configures the pin as an input and the pulldown device is activated for a pin, it will also load the input to the other module.
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Parallel Input/Output
4. If interaction between the port logic and the other module is not desired, the pin should be configured as an input by clearing the appropriate DDRB bit. The input pulldown device is disabled by clearing the appropriate PDRB bit (or by disabling programmable pulldowns with the SWPDI bit in the MOR).
7.4.6 PB4/AN4/TCMP/CMP1 Logic The PB4/AN4/TCMP/CMP1 pin can be used as a simple I/O port pin, be controlled by the OLVL bit from the output compare function of the 16-bit programmable timer, or be controlled directly by the output of comparator 1 as shown in Figure 7-9. The PB4 data, the programmable timer OLVL bit, and the output of comparator 1 are all logically ORed together to drive the pin. Also, the analog subsystem input channel 4 multiplexer is connected directly to this pin. The operations of PB4 pin are summarized in Table 7-2.
READ $0005 WRITE $0005 DATA DIRECTION REGISTER B BIT DDRB4
ANALOG SUBSYSTEM INPUT AN4 AND TIMER OUTPUT COMPARE
R INTERNAL DATA BUS
WRITE $0001
PORT BDATA REGISTER BIT PB4 OLVL (TIMER OUTPUT COMPARE) CMP1 (COMPARATOR 1 OUT)
PB4 AN4 TCMP HIGH SINK/ SOURCE CURRENT CAPABILITY
READ $0001 PULLDOWN REGISTER B BIT PDIB4
WRITE $0011 R RESET
SWPDI
PULLDOWN DEVICE
MASK OPTION REG. ($1FF1) OPT COP REGISTER ($1FF0)
Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit
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Parallel Input/Output Port B
When using the PB4/AN4/TCMP/CMP1 pin, these interactions must be noted: 1. If the OLVL timer output compare function is the required output function, then the DDRB4 bit must be set, the PB4 data bit must be cleared, and the OPT bit in the COPR must be cleared. The PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the OLVL bit. The pulldown device will be disabled in this case. The analog subsystem would not normally use this pin as an analog input in this case. 2. If the PB4 data bit is the required output function, then the DDRB4 bit must be set, the OLVL bit in the TCR must be cleared, and the OPT bit in the COPR must be cleared. The pulldown device will be disabled in this case. The analog subsystem would not normally use this pin as an analog input in this case. 3. If the comparator 1 output is the desired output function, then the PB4 data bit must be cleared, the DDRB4 bit must be set, the OLVL bit in the TCR must be cleared, and the OPT bit in the COPR must be set. The PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the OLVL bit. The pulldown device will be disabled in this case. The analog subsystem would not normally use this pin as an analog input in this case. 4. If the PB4 pin is to be an input to the analog subsystem or a digital input, then the DDRB4 bit must be cleared. In this case, the PB4 pin can still be read, but the voltage present will be returned as a binary value. Depending on the external application, the PB4 pulldown may also be disabled by setting the PDIB4 pulldown inhibit bit. In this case, both the digital and analog functions connected to this pin can be utilized.
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Table 7-2. Port B Pin Functions -- PB0-PB4
Control Bits Port B Pin Comparator 1 Timer SWPDI in MOR 0 PB0 PB1 PB2 PB3 0 X(2) X(2) X(2) X(2) 1 X(2) 0 X(2) X(2) PB4 X(2) 0 X(2) 1 X(2) X(2) 0 1 X(2) 1 X(2) X(2) 0 1 0 1 1 X(2) 1 0 0 0 1 X(2) X(2) X(2) X(2) X(2) X(2) Port B PDIBx DDRBx(1) 0 1 X(2) X(2) 0 1 X(2) X(2) X(2) X(2) X(2) X(2) 0 0 0 1 0 0 0 1 1 1 1 1 PORTB Access (Pin or Data Register) Read Pin Pin Pin Data Pin Pin Pin Data Data Data 1 1 Result on Port B Pins Pin PBx in PBx in PBx in PBx out PB4 in PB4 in PB4 in PB4 out PB4 out PB4 out 1 1
.
CMP1 COE1 OPT in COPR OLVL
Write Pulldown Data Data Data Data Data Data Data Data Data Data Data Data On Off Off Off On Off Off Off Off Off Off Off
1. DDRB can always be read or written. 2. Don't care
7.4.7 PB5/SDO Logic The PB5/SDO pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as shown in Figure 7-10. The operations of the PB5 pin are summarized in Table 7-3. When using the PB5/SDO pin, these interactions must be noted: 1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB5/SDO pin buffer to be enabled and to be driven by the serial data output (SDO) from the SIOP. The pulldown device will be disabled in this case. 2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5 and PB5 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB5 bit is cleared, reading the PB5 data register will return the current state of the PB5/SDO pin.
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Parallel Input/Output Port B
SERIAL DATA OUT (SDO) SERIAL ENABLE (SPE) READ $0005 WRITE $0005 R INTERNAL DATA BUS DATA DIRECTION REGISTER B BIT DDRB5 VDD
WRITE $0001
PORT B DATA REGISTER BIT PB5
PB5 SDO
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIB5 PULLDOWN DEVICE SWPDI MASK OPTION REG. ($1FF1)
R RESET
Figure 7-10. PB5/SDO Pin I/O Circuit 3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored in the DDRB5, PDIB5, and PB5 register bits will then control the PB5/SDO pin. 4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in the SCR and the DDRB5 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB5 pulldown inhibit bit. 5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the SCR must be cleared and the PDIB5 bit must be set. The pulldown device will be disabled in this case.
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7.4.8 PB6/SDI Logic The PB6/SDI pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as shown in Figure 7-11. The operations of PB6/SDI pin are summarized in Table 7-3.
SERIAL DATA IN (SDI) SERIAL ENABLE (SPE) READ $0005 WRITE $0005 R INTERNAL DATA BUS
DATA DIRECTION REGISTER B BIT DDRB6
WRITE $0001
PORT B DATA REGISTER BIT PB6
PB6 SDI
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIB6 PULLDOWN DEVICE SWPDI MASK OPTION REG. ($1FF1)
R RESET
Figure 7-11. PB6/SDI Pin I/O Circuit When using the PB6/SDI pin, these interactions must be noted: 1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB6/SDI pin buffer to be disabled to allow the PB6/SDI pin to act as an input that feeds the serial data input (SDI) of the SIOP. The pulldown device is disabled in this case. 2. If the SIOP function is in control of the PB6/SDI pin, the DDRB6 and PB6 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB6 bit is cleared, reading the PB6 data register will return the current state of the PB6/SDI pin.
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Parallel Input/Output Port B
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored in the DDRB6, PDIB6, and PB6 register bits will then control the PB6/SDI pin. 4. If the PB6/SDI pin is to be a digital input, then both the SPE bit in the SCR and the DDRB6 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB6 pulldown inhibit bit. 5. If the PB6/SDI pin is to be a digital output, then the SPE bit in the SCR must be cleared and the DDRB6 bit must be set. The pulldown device will be disabled in this case.
7.4.9 PB7/SCK Logic The PB7/SCK pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as shown in Figure 7-12. The operations of the PB7/SCK pin are summarized in Table 7-3.
SERIAL DATA CLOCK (SCK) CLOCK SOURCE (MSTR) SERIAL ENABLE (SPE) READ $0005 WRITE $0005 INTERNAL DATA BUS R DATA DIRECTION REGISTER B BIT DDRB7
WRITE $0001
PORT B DATA REGISTER BIT PB7
PB7 SCK
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIB7 PULLDOWN DEVICE SWPDI MASK OPTION REG. ($1FF1)
R RESET
Figure 7-12. PB7/SCK Pin I/O Circuit
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When using the PB7/SCK pin, these interactions must be noted: 1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB7/SCK pin buffer to be controlled by the MSTR control bit in the SCR. The pulldown device is disabled in these cases. a. If the MSTR bit is set, then the PB7/SCK pin buffer will be enabled and driven by the serial data clock (SCK) from the SIOP. b. If the MSTR bit is clear, then the PB7/SCK pin buffer will be disabled, allowing the PB7/SCK pin to drive the serial data clock (SCK) into the SIOP. 2. If the SIOP function is in control of the PB7/SCK pin, the DDRB7 and PB7 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB7 bit is cleared, reading the PB7 data register will return the current state of the PB7/SCK pin. 3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored in the DDRB7, PDIB7, and PB7 register bits will then control the PB7/SCK pin. 4. If the PB7/SCK pin is to be a digital input, then both the SPE bit in the SCR and the DDRB7 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB7 pulldown inhibit bit. 5. If the PB7/SCK pin is to be a digital output, then the SPE bit in the SCR must be cleared and the DDRB7 bit must be set. The pulldown device will be disabled when the pin is set as an output.
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Parallel Input/Output Port C (28-Pin Versions Only)
Table 7-3. Port B Pin Functions -- PB5-PB7
Control Bits Port B Pin SIOP SPE MSTR SWPDI in MOR 0 0 PB5 1 X(2) X(2) 0 1 X
(2)
Port B PDIBx 0 1 X X
(2)
PORTB Access (Pin or Data Register) Read Pin Pin Pin Data SDO Data Pin Pin Pin Data SDI Data Pin Pin Pin Data SCK Data SCK Data Write Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1
Result on Port B Pins Pulldown On Off Off Off Off Off On Off Off Off Off Off On Off Off Off Off Off Off Off Pin PB5 in PB5 in PB5 in PB5 out SDO out SDO out PB6 in PB6 in PB6 in PB6 out SDI in SDI in PB7 in PB7 in PB7 in PB7 out SCK in SCK in SCK out SCK out
DDRBx(1)
X(2) 0 0
X(2) 0 1 X
(2)
0 PB6 1
X(2)
1 X(2)
X(2) X(2) 0 1 X(2) X
(2)
X(2)
X(2)) 0
0 PB7
X(2)
0 1 X
(2)
0 1 1
X(2) X(2)
X(2) X(2)
1. DDRB can always be read or written. 2. Don't care
7.5 Port C (28-Pin Versions Only)
Port C is an 8-bit, general-purpose, bidirectional I/O port with these features: * * * Individual programmable pulldown devices High current sinking capability on all port C pins, with a maximum total for port C High current sourcing capability on all port C pins, with a maximum total for port C
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7.5.1 Port C Data Register The port C data register (PORTC) contains a bit for each of the port C pins. When a port C pin is programmed to be an output, the state of its data register bit determines the state of the output pin. When a port C pin is programmed to be an input, reading the port C data register returns the logic state of the pin.
Address: $0002 Bit 7 Read: PC7 Write: Reset: Unaffected by reset PC6 PC5 PC4 PC3 PC2 PC1 PC0 6 5 4 3 2 1 Bit 0
Figure 7-13. Port C Data Register (PORTC) PC7-PC0 -- Port C Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in the port C data direction register (DDRC). Reset has no effect on port C data.
7.5.2 Data Direction Register C The contents of the port C data direction register (DDRC) determine whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the associated port C pin. A DDRC bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRC bit disables the output buffer for the associated port C pin. A reset initializes all DDRC bits to logic 0s, configuring all port C pins as inputs.
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Parallel Input/Output Port C (28-Pin Versions Only)
Address:
$0006 Bit 7 6 DDRC6 0 5 DDRC5 0 4 DDRC4 0 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0
Read: DDRC7 Write: Reset: 0
Figure 7-14. Data Direction Register C (DDRC) DDRC7-DDRC0 -- Port C Data Direction Bits These read/write bits control port C data direction. Reset clears the DDRC7-DDRC0 bits. 1 = Corresponding port C pin configured as output and pulldown device disabled 0 = Corresponding port C pin configured as input
7.5.3 Port C Pulldown Devices All port C pins can have software programmable pulldown devices enabled or disabled globally by the SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown register A (PDRA) shown in Figure 7-3. PDICH controls the upper four pins (PC7-PC4) and PDICL controls the lower four pins (PC3-PC0). Clearing the PDICH or PDICL bits in the PDRA turns on the pulldown devices if the port C pin is an input. Reading the PDRA returns undefined results since it is a write-only register. Reset clears the PDICH and PDICL bits, which turns on all the port C pulldown devices.
7.5.4 Port C Logic Figure 7-15 shows the I/O logic of port C. When a port C pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. When a port C pin is programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDR bit. Table 7-4 summarizes the operations of the port C pins.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Parallel Input/Output Advance Information 103
Parallel Input/Output
READ $0006 WRITE $0006 DATA DIRECTION REGISTER C BIT DDRCx
R
INTERNAL DATA BUS
WRITE $0002
PORT C DATA REGISTER BIT PCx
PCx
READ $0002 WRITE $0010 PULLDOWN REGISTER A BIT PDICx
HIGH SINK/SOURCE CURRENT CAPABILITY PULLDOWN DEVICE
R RESET
Figure 7-15. Port C I/O Circuit Table 7-4. Port C Pin Functions (28-Pin Versions Only)
Control Bits Port C Pin(s) SWPDI in MOR 0 PC0 PC1 PC2 PC3 0 1 X(2) 0 PC4 PC5 PC6 PC7 0 1 X(2) Port C PDICH X(2) X(2) X X(2) 0 1 X X(2) PDICL 0 1 X(2) X(2) X(2) X(2) X(2) X(2) DDRCx(1) 0 0 0 1 0 0 0 1 PORTC Access (Pin or Data Register) Read Pin Pin Pin Data Pin Pin Pin Data Write Data Data Data Data Data Data Data Data Result on Port C Pins Pulldown On Off Off Off On Off Off Off Pin PCx in PCx in PCx in PCx out PCx in PCx in PCx in PCx out
1. DDRC can always be read or written. 2. Don't care
Advance Information 104 Parallel Input/Output
SWPDI MASK OPTION REGISTER ($1FF1)
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Parallel Input/Output Port Transitions
7.6 Port Transitions
Glitches and temporary floating inputs can occur if the control bits regarding each port I/O pin are not performed in the correct sequence. * * Do not use read-modify-write instructions on pulldown register A or B. Avoid glitches on port pins by writing to the port data register before changing data direction register bits from a logic 0 to a logic 1. Avoid a floating port input by clearing its pulldown register bit before changing its data direction register bit from a logic 1 to a logic 0. The SWPDI bit in the MOR turns off all port pulldown devices and disables software control of the pulldown devices. Reset has no effect on the pulldown devices when the SWPDI bit is set. Two or more output pins of the same port can be connected electrically to provide output currents up to the sum of the maximum specified drive currents as defined in 15.8 DC Electrical Characteristics (5.0 Vdc) and 15.9 DC Electrical Characteristics (3.0 Vdc). Care must be taken to ensure that all ganged pins always maintain the same output logic value.
*
*
*
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Parallel Input/Output
Advance Information 105
Parallel Input/Output
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Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 8. Analog Subsystem
8.1 Contents
8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Analog Multiplex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Analog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.7 Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . . 132 8.7.1 Absolute Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . . 133 8.7.1.1 Internal Absolute Reference . . . . . . . . . . . . . . . . . . . . . 133 8.7.1.2 External Absolute Reference . . . . . . . . . . . . . . . . . . . . . 134 8.7.2 Ratiometric Voltage Readings . . . . . . . . . . . . . . . . . . . . . . 134 8.7.2.1 Internal Ratiometric Reference . . . . . . . . . . . . . . . . . . .135 8.7.2.2 External Ratiometric Reference . . . . . . . . . . . . . . . . . . . 136 8.8 Voltage Comparator Features . . . . . . . . . . . . . . . . . . . . . . . . 136 8.8.1 Voltage Comparator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.8.2 Voltage Comparator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.9 8.10 8.11 8.12 8.13 8.14 8.15 Current Source Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Internal Temperature Sensing Diode Features. . . . . . . . . . . . 138 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Port B Interaction with Analog Inputs . . . . . . . . . . . . . . . . . . .139 Port B Pins as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Port B Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Noise Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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Analog Subsystem
8.2 Introduction
The analog subsystem of the MC68HC705JJ7/MC68HC705JP7 is based on two on-chip voltage comparators and a selectable current charge/discharge function as shown in Figure 8-1. This configuration provides several features: * * Two independent voltage comparators with external access to both inverting and non-inverting inputs One voltage comparator can be connected as a single-slope analog-to-digital (A/D) and the other connected as a single-voltage comparator. The possible single-slope A/D connection provides these features: - A/D conversions can use VDD or an external voltage as a reference with software used to calculate ratiometric or absolute results - Channel access of up to four inputs via multiplexer control with independent multiplexer control allowing mixed input connections - Access to VDD and VSS for calibration - Divide by 2 to extend input voltage range - Each comparator can be inverted to calculate input offsets. - Internal sample and hold capacitor - Direct digital output of comparator 1 to the PB4 pin Voltages are resolved by measuring the time it takes an external capacitor to charge up to the level of the unknown input voltage being measured. The beginning of the A/D conversion time can be started by several means: * * * Output compare from the 16-bit programmable timer Timer overflow from the 16-bit programmable timer Direct software control via a register bit
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Analog Subsystem Introduction
PB3/AN3/TCAP OCF ICF VDD PORTB LOGIC PB0 AN0 VDD IDISCHG CP2EN + - INTERNAL TEMPERATURE DIODE INV CP1EN CPIE VDD COMPARATOR INPUT SELECT AND SAMPLE CONTROL COMP2 ICHG CHG CHARGE CURRENT CONTROL LOGIC ATD1 ATD2 ISEN CP2EN ICEN
2 TO 1 MUX
TCAP
$001D ANALOG INTERRUPT
80 k VREF
CPF2 ANALOG STATUS REGISTER (ASR) CPF1 CMP2 CMP1 VOFF INTERNAL HC05 BUS
PORTB LOGIC PB1 AN1 PORTB LOGIC PB2 AN2 PORTB LOGIC PB3 AN3 TCAP PORTB LOGIC PB4 AN4 TCMP MUX4 VAOFF VSS MUX3 MUX2 CHANNEL SELECT BUS MUX1
80 k
SAMPLE CAP
100 MV OFFSET
-+
$001E CP1EN OPT (COPR) HOLD DHOLD INV VREF INV VREF MUX4 MUX3 MUX2 ANALOG MUX REGISTER (AMUX) $0003 DENOTES INTERNAL ANALOG VSS
+ -
COMP1
OLVL
-+
VSS AVSS = VSS = VAOFF
PORT B CONTROL LOGIC
COE1 OPT (COPR) MUX4 MUX3 MUX2 MUX1
MUX1
Figure 8-1. Analog Subsystem Block Diagram
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ANALOG CONTROL REGISTER (ACR)
16-BIT PROG. TIMER
TOF
Analog Subsystem
The end of the A/D conversion time can be captured by these means: * * * Input capture in the 16-bit programmable timer Interrupt generated by the comparator output Software polling of the comparator output using software loop time
8.3 Analog Multiplex Register
The analog multiplex register (AMUX) controls the general interconnection and operation. The control bits in the AMUX are shown in Figure 8-2.
Address: $0003 Bit 7 Read: HOLD Write: Reset: 1 0 0 0 0 0 0 0 DHOLD INV VREF MUX4 MUX3 MUX2 MUX1 6 5 4 3 2 1 Bit 0
Figure 8-2. Analog Multiplex Register (AMUX) HOLD, DHOLD These read/write bits control the source connection to the negative input of voltage comparator 2 shown in Figure 8-3. This allows the voltage on the internal temperature sensing diode, the channel selection bus, or the divide-by-two channel selection bus to charge the internal sample capacitor and to also be presented to comparator 2. The decoding of these sources is given in Table 8-1. During the hold case when both the HOLD and DHOLD bits are clear, the VOFF bit in the analog status register (ASR) can offset the VSS reference on the sample capacitor by approximately 100 mV. This offset source is bypassed whenever the sample capacitor is being charged with either the HOLD or DHOLD bit set. The VOFF bit must be enabled by the OPT bit in the COPR at location $1FF0.
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MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Analog Subsystem Analog Multiplex Register
VDD PB0 INTERNAL TEMPERATURE DIODE CHANNEL SELECTION BUS
+ -
COMP2
80 k
80 k
SAMPLE CAP
VOFF OPT (MOR) VSS OFFSET HOLD
+
DHOLD
Figure 8-3. Comparator 2 Input Circuit
Table 8-1. Comparator 2 Input Sources
Case HOLD (AMUX) DHOLD (AMUX) OPT (MOR) 0 Hold sample voltage 1 0 0 1 1 Yes VOFF (ASR) X(1) No 0 Voltage Offset Source To Negative Input of Comparator 2 Sample capacitor connected to comparator 2 negative input; very low leakage current. Sample capacitor connected to comparator 2 negative input; bottom of capacitor offset from VSS by approximately 100 mV, very low leakage current. Signal on channel selection bus is divided by 2 and connected to sample capacitor and comparator 2 negative input Signal on channel selection bus is connected directly to sample capacitor and comparator 2 negative input. Internal temperature sensing diode connected directly to sample capacitor and comparator 2 negative input.
Divide input
0
1
X(1)
X(1)
-
No
Direct input Internal temperature diode
1. Don't care
1
0
X(1)
X(1)
No
1
1
X(1)
X(1)
No
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Analog Subsystem
During a reset, the HOLD bit is set and the DHOLD bit is cleared, which connects the internal sample capacitor to the channel selection bus. And since a reset also clears the MUX[1:4] bits, then the channel selection bus will be connected to VSS and the internal sample capacitor will be discharged to VSS following the reset.
NOTE:
When sampling a voltage for later conversion, the HOLD and DHOLD bits should be cleared before making any changes in the MUX channel selection. If the MUX channel and the HOLD/DHOLD are changed on the same write cycle to the AMUX register, the sampled voltage may be altered during the channel switching. INV This is a read/write bit that controls the relative polarity of the inherent input offset voltage of the voltage comparators. This bit allows voltage comparisons to be made with both polarities and then averaged together by taking the sum of the two readings and then dividing by 2 (logical shift right). The polarity of the input offset is reversed by interchanging the internal voltage comparator inputs while also inverting the comparator output. This interchange does not alter the action of the voltage comparator output with respect to its port pins. That is, the output will only go high if the voltage on the positive input (PB2 pin for comparator 1 and PB0 pin for comparator 2) is above the voltage on the respective negative input (PB3 pin for comparator 1 and PB1 pin for comparator 2). This is shown schematically in Figure 8-4. This bit is cleared by a reset of the device. 1 = The voltage comparators are internally inverted. 0 = The voltage comparators are not internally inverted.
NOTE:
The effect of changing the state of the INV bit is to only change the polarity of the input offset voltage. It does not change the output phase of the CPF1 or CPF2 flags with respect to the external port pins.
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Analog Subsystem Analog Multiplex Register
V+
VIO
RISE WHEN V+ > V-
V+
VIO
RISE WHEN V+ > V-
+ COMP - V-
INV = 0
+ COMP -
V-
INV = 1
Figure 8-4. INV Bit Action
NOTE:
Either comparator may generate an output flag when the inputs are exchanged due to a change in the state of the INV bit. It is therefore recommended that the INV bit not be changed while waiting for a comparator flag. Further, any changes to the state of the INV bit should be followed by writing a logic 1 to both the CPFR1 and CPFR2 bits to clear any extraneous CPF1 or CPF2 flags that may have occurred. VREF This read/write bit connects the channel select bus to VDD for making a reference voltage measurement. It cannot be selected if any of the other input sources to the channel select bus are selected as shown in Table 8-2. This bit is cleared by a reset of the device. 1 = Channel select bus connected to VDD if all MUX1:4 are cleared. 0 = Channel select bus cannot be connected to VDD. MUX1:4 These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage comparator 2 for purposes of making a voltage measurement. They can be selected individually or combined with any of the other input sources to the channel select bus as shown in Table 8-2.
NOTE:
The VAOFF voltage source shown in Figure 8-1 depicts a small offset voltage generated by the total chip current passing through the package bond wires and lead frame that are attached to the single VSS pin. This offset raises the internal VSS reference (AVSS) in the analog subsystem
Advance Information Analog Subsystem 113
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Analog Subsystem
with respect to the external VSS pin. Turning on the VSS MUX to the channel select bus connects it to this internal AVSS reference line. When making A/D conversions, this AVSS offset gets placed on the external ramping capacitor since the discharge device on the PB0/AN0 pin discharges the external capacitor to the internal AVSS line. Under these circumstances, the positive input (+) to comparator 2 will always be higher than the negative input (-) until the negative input reaches the AVSS offset voltage plus any offset in comparator 2. Therefore, input voltages cannot be resolved if they are less than the sum of the AVSS offset and the comparator offset, because they will always yield a low output from the comparator. Table 8-2. Channel Select Bus Combinations
Analog Multiplex Register VREF 0 X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) X(1) MUX4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MUX3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MUX2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MUX1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VDD Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi Z Channel Select Bus Connected to: PB4/AN4/ TCMP Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z On On On On On On On On PB3/AN3/ TCAP Hi-Z Hi-Z Hi-Z Hi-Z On On On On Hi-Z Hi-Z Hi-Z Hi-Z On On On On PB2/AN2 Hi-Z Hi-Z On On Hi-Z Hi-Z On On Hi-Z Hi-Z On On Hi-Z Hi-Z On On PB1/AN1 Hi-Z On Hi-Z On Hi-Z On Hi-Z On Hi-Z On Hi-Z On Hi-Z On Hi-Z On VSS On Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi Z
1. Don/t care
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Analog Subsystem Analog Control Register
8.4 Analog Control Register
The analog control register (ACR) controls the power-up, interrupt, and flag operation. The analog subsystem draws current while it is operating. The resulting power consumption can be reduced by powering down the analog subsystem when not in use (refer to 15.6 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc)). This can be done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in the ACR at $001D. Since these bits are cleared following a reset, the voltage comparators and the charge current source will be powered down following a reset of the device. The control bits in the ACR are shown in Figure 8-5. All the bits in this register are cleared by a reset of the device.
Address: $001D Bit 7 Read: Write: Reset: CHG 0 6 ATD2 0 5 ATD1 0 4 ICEN 0 3 CPIE 0 2 CP2EN 0 1 CP1EN 0 Bit 0 ISEN 0
Figure 8-5. Analog Control Register (ACR) CHG The CHG enable bit allows direct control of the charge current source and the discharge device and also reflects the state of the discharge device. This bit is cleared by a reset of the device. 1 = If the ISEN bit is also set, the charge current source is sourcing current out of the PB0/AN0 pin. Writing a logic 1 enables the charging current out of the PB0/AN0 pin. 0 = The discharge device is sinking current into the PB0/AN0 pin. Writing a logic 0 disables the charging current and enables the discharging current into the PB0/AN0 pin, if the ISEN bit is also set.
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Analog Subsystem
ATD1-ATD2 The ATD1-ATD2 enable bits select one of the four operating modes used for making A/D conversions via the single-slope method.These four modes are given in Table 8-3. These bits have no effect if the ISEN enable bit is cleared. These bits are cleared by a reset of the device and thereby return the analog subsystem to the manual A/D conversion method. Table 8-3. A/D Conversion Options
A/D Option Mode Charge Control Current source and discharge disabled A/D Options ISEN ATD2 ATD1 CHG Current Flow to/from PB0/AN0
Disabled
0
X
X
X
Current control disabled, no source or sink current Begin sourcing current when the CHG bit is set and continue to source current until the CHG bit is cleared. The CHG bit remains set until the next time ICF occurs. The CHG bit remains cleared until the next time OCF occurs. The CHG bit remains set until the next time ICF occurs.
1
0
0
1
1
1
0
1
3
Automatic charge and discharge (OCF-ICF) synchronized to timer
1
1
1
0
1
1
1
1
ICEN This is a read/write bit that enables a voltage comparison to trigger the input capture register of the programmable timer when the CPF2 flag bit is set. Therefore, an A/D conversion could be started by receiving an OCF or TOF from the programmable timer and then terminated when the voltage on the external ramping capacitor reaches the level of the unknown voltage. The time of termination will be stored in the
Advance Information 116 Analog Subsystem MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Analog Subsystem Analog Control Register
16-bit buffer located at $0014 and $0015. This bit is automatically set whenever mode 2 or 3 is selected by setting the ATD2 control bit. This bit is cleared by a reset of the device. 1 = Connects the CPF2 flag bit to the timer input capture register 0 = Connects the PB3/AN3 pin to the timer input capture register
NOTE:
For the input capture to occur when the output of comparator 2 goes high, the IEDG bit in the TCR must also be set. When the ICEN bit is set, the input capture function of the programmable timer is not connected to the PB3/AN3/TCAP pin but is driven by the CPF2 output flag from comparator 2. To return to capturing times from external events, the ICEN bit must first be cleared before the timed event occurs. CPIE This is a read/write bit that enables an analog interrupt when either of the CPF1 or CPF2 flag bits is set to a logic 1. This bit is cleared by a reset of the device. 1 = Enables analog interrupts when comparator flag bits are set 0 = Disables analog interrupts when comparator flag bits are set
NOTE:
If both the ICEN and CPIE bits are set, they will both generate an interrupt by different paths. One will be the programmable timer interrupt due to the input capture and the other will be the analog interrupt due to the output of comparator 2 going high. In this case, the input capture interrupt will be entered first due to its higher priority. The analog interrupt will then need to be serviced even if the comparator 2 output has been reset or the input capture flag (ICF) has been cleared. CP2EN The CP2EN enable bit controls power to voltage comparator 2 in the analog subsystem. Powering down a comparator will drop the supply current. This bit is cleared by a reset of the device. 1 = Writing a logic 1 powers up voltage comparator 2. 0 = Writing a logic 0 powers down voltage comparator 2.
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Analog Subsystem
NOTE:
Voltage comparators power up slower than digital logic and their outputs may go through indeterminate states which might set their respective flags (CPF1, CPF2). It is therefore recommended to power up the charge current source first (ISEN), then to power up any comparators, and finally clear the flag bits by writing a logic 1 to the respective CPFR1 or CPFR2 bits in the ACR. CP1EN The CP1EN enable bit will power down the voltage comparator 1 in the analog subsystem. Powering down a comparator will drop the supply current. This bit is cleared by a reset of the device. 1 = Writing a logic 1 powers up voltage comparator 1 0 = Writing a logic 0 powers down voltage comparator 1 ISEN The ISEN enable bit will power down the charge current source and disable the discharge device in the analog subsystem. Powering down the current source will drop the supply current by about 200 A. This bit is cleared by a reset of the device. 1 = Writing a logic 1 powers up the ramping current source and enables the discharge device on the PB0/AN0 pin. 0 = Writing a logic 0 powers down the ramping current source and disables the discharge device on the PB0/AN0 pin.
NOTE:
The analog subsystem has support circuitry which draws current. This current will be powered down if both comparators and the charge current source are powered down (ISEN, CP1EN, and CP2EN all cleared). Powering up either comparator or the charge current source will activate the support circuitry.
Advance Information 118 Analog Subsystem
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Analog Subsystem Analog Status Register
8.5 Analog Status Register
The analog status register (ASR) contains status and control of the comparator flag bits. These bits in the ASR are shown in Figure 8-6. All the bits in this register are cleared by a reset of the device.
Address: Read: Write: Reset: 0 0 $001E Bit 7 CPF2 6 CPF1 5 0 CPFR2 0 = Unimplemented 4 0 CPFR1 0 3 COE1 0 R 2 VOFF 0 = Reserved 1 CMP2 0 Bit 0 CMP1 R 0
Figure 8-6. Analog Status Register (ASR) CPF2 This read-only flag bit is edge sensitive to the rising output of comparator 2. It is set when the voltage on the PB0/AN0 pin rises above the voltage on a sample capacitor which creates a positive edge on the output of comparator 2, regardless of the state of the INV bit in the AMUX register. This bit is reset by writing a logic 1 to the CPFR2 reset bit in the ASR. This bit is cleared by a reset of the device. 1 = A positive transition on the output of comparator 2 has occurred since the last time the CPF2 flag has been cleared. 0 = A positive transition on the output of comparator 2 has not occurred since the last time the CPF2 flag has been cleared. CPF1 This read-only flag bit is edge sensitive to the rising output of comparator 1. It is set when the voltage on the PB2/AN2 pin rises above the voltage on the PN3/AN3/TCAP pin which creates a positive edge on the output of comparator 1, regardless of the state of the INV bit in the AMUX register. This bit is reset by writing a logic 1 to the CPFR1 reset bit in the ASR. This bit is cleared by a reset of the device. 1 = A positive transition on the output of comparator 1 has occurred since the last time the CPF1 flag has been cleared. 0 = A positive transition on the output of comparator 1 has not occurred since the last time the CPF1 flag has been cleared.
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Analog Subsystem
CPFR2 Writing a logic 1 to this write-only flag clears the CPF2 flag in the ASR. Writing a logic 0 to this bit has no effect. Reading the CPFR2 bit will return a logic 0. By default, this bit looks cleared following a reset of the device. 1 = Clears the CPF2 flag bit 0 = No effect CPFR1 Writing a logic 1 to this write-only flag clears the CPF1 flag in the ASR. Writing a logic 0 to this bit has no effect. Reading the CPFR1 bit will return a logic 0. By default, this bit looks cleared after a reset of the device. 1 = Clears the CPF1 flag bit 0 = No effect
NOTE:
The CPFR1 and CPFR2 bits should be written with logic 1s following a power-up of either comparator. This will clear out any latched CPF1 or CPF2 flag bits which might have been set during the slower power-up sequence of the analog circuitry. If both inputs to a comparator are above the maximum common-mode input voltage (VDD -1.5 V), the output of the comparator is indeterminate and may set the comparator flag. Applying a reset to the device may only temporarily clear this flag as long as both inputs of a comparator remain above the maximum common-mode input voltages. VOFF This read-write bit controls the addition of an offset voltage to the bottom of the sample capacitor. It is not active unless the OPT bit in the COPR at location $1FF0 is set. Any reads of the VOFF bit location return a logic 0 if the OPT bit is clear. During the time that the sample capacitor is connected to an input (either HOLD or DHOLD set), the bottom of the sample capacitor is connected to VSS. The VOFF bit is cleared by a reset of the device. For more information, see 8.11 Sample and Hold. 1 = Enables approximately 100 mV offset to be added to the sample voltage when both the HOLD and DHOLD control bits are cleared 0 = Connects the bottom of the sample capacitor to VSS
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Analog Subsystem Analog Status Register
COE1 This read-write bit controls the output of comparator 1 to the PB4 pin. It is not active unless the OPT bit in the COPR at location $1FF0 is set. Any reads of the COE1 bit location return a logic 0 if the OPT bit is clear. The COE1 bit is cleared by a reset of the device. 1 = Enables the output of comparator 1 to be ORed with the PB4 data bit and OLVL bit, if the DDRB4 bit is also set 0 = Disables the output of comparator 1 from affecting the PB4 pin CMP2 This read-only bit shows the state of comparator 2 during the time that the bit is read. This bit is therefore the current state of the comparator without any latched history. The CMP2 bit will be high if the voltage on the PB0/AN0 pin is greater than the voltage on the PB1/AN1 pin, regardless of the state of the INV bit in the AMUX register. Since a reset disables comparator 2, this bit returns a logic 0 following a reset of the device. 1 = The voltage on the positive input on comparator 2 is higher than the voltage on the negative input of comparator 2. 0 = The voltage on the positive input on comparator 2 is lower than the voltage on the negative input of comparator 2. CMP1 This read-only bit shows the state of comparator 1 during the time that the bit is read. This bit is therefore the current state of the comparator without any latched history. The CMP1 bit will be high if the voltage on the PB2/AN2 pin is greater than the voltage on the PB3/AN3/TCAP pin, regardless of the state of the INV bit in the AMUX register. Since a reset disables comparator 1, this bit returns a logic 0 following a reset of the device. 1 = The voltage on the positive input on comparator 1 is higher than the voltage on the negative input of comparator 1. 0 = The voltage on the positive input on comparator 1 is lower than the voltage on the negative input of comparator 1.
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8.6 A/D Conversion Methods
The control bits in the ACR provide various options to charge or discharge current through the PB0/AN0 pin to perform single-slope A/D conversions using an external capacitor from the PB0/AN0 pin to VSS as shown in Figure 8-7. The various A/D conversion triggering options are given in Table 8-3. C x VX I
VDD -1.5 Vdc
Charge Time =
UNKNOWN VOLTAGE ON (-) INPUT VOLTAGE ON CAPACITOR CONNECTED TO (+) INPUT CHARGE TIME TO MATCH UNKNOWN MAXIMUM CHARGE TIME TO VDD -1.5 Vdc +5V PB4/AN4 UNKNOWN OR REFERENCE SIGNALS PB3/AN3 PB2/AN2 PB1/AN1 RAMP CAP PB0/AN0 MC68HC705JJ7 MC68HC705JP7 VSS VDD
DISCHARGE TIME TO RESET CAPACITOR
Figure 8-7. Single-Slope A/D Conversion Method The top three bits of the ACR control the charging and discharging current into or out of the PB0/AN0 pin. These three bits will have no effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing of the ISEN bit will immediately disable both the charge current source and the discharge device. Since all these bits and the ISEN bit are
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cleared when the device is reset, the MC68HC705JJ7/MC68HC705JP7 starts with the charge and discharge function disabled. The length of time required to reach the maximum voltage to be measured and the speed of the time counting mechanism will determine the resolution of the reading. The time to ramp the external capacitor voltage to match the maximum voltage is dependent on: * * * * * Charging current to external capacitor Value of the external capacitor Clock rate for timing function Any prescaling of the clock to the timing function Desired resolution
The charging behavior is described by the general equation: tCHG = CEXT x VX / ICHG Where: tCHG = Charge time (seconds)
CEXT = Capacitance (F) VX ICHG = Unknown voltage (volts) = Charge current (A)
Since the MCU can measure time in a variety of ways, the resolution of the conversion will depend on the length of the time keeping function and its prescaling to the oscillator frequency (fOSC). Therefore, the charge time also equals: tCHG = P x N / fOSC Where: P N fOSC = Prescaler value (/ 2, / 4, / 8, etc.) = Number of counts during charge time = Oscillator clock frequency (Hz)
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NOTE:
Noise on the system ground or the external ramping capacitor can cause the comparator to trip prematurely. Therefore, in any given application it is best to use the fastest possible ramp rate (shortest charge time). The previous two equations for the charge time, tCHG, can be combined to form the following expression for the full scale count (NFS) of the measured time versus the full scale unknown voltage (VFS): NFS = CEXT x VFS x fOSC / (P x ICHG) Since a given timing method has a fixed charge current and prescaler, then the variation in the resultant count for a given unknown voltage is mainly dependent on the operating frequency and the capacitance value used. The desired external capacitance for a given voltage range, fOSC, conversion method, and resolution is defined as: CEXT = NFS x P x ICHG / (VFS x fOSC)
NOTE:
The value of any capacitor connected directly to the PB0/AN0 pin should be limited to less than 2 microfarads. Larger capacitances will create high discharge currents which may damage the device or create signal noise. The full scale voltage range for a given capacitance, fOSC, conversion method, and resolution is defined as: VFS = NFS x P x ICHG / (CEXT x fOSC) Once charged to a given voltage, a finite amount of time will be required to discharge the capacitor back to its start voltage at VSS. This discharge time will be solely based on the value of capacitance used and the sinking current of the internal discharge device. To allow a reasonable time for the capacitor to return to VSS levels, the discharge time should last about 10 milliseconds per microfarad of capacitance attached to the PB0 pin. If the total charge/discharge cycle time is critical, then the discharge time should be at least 1/10 of the most recent charge time. Shorter discharge times may be used if lesser accuracy in the voltage measurement is acceptable.
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NOTE:
Sufficient time should be allowed to discharge the external capacitor or subsequent charge times will be shortened with resultant errors in timing conversion. Table 8-4 gives the range of values of each parameter in the A/D timing conversion and Table 8-5 gives some A/D conversion examples for several bit resolutions. The mode selection bits in the ACR allow four methods of single-slope A/D conversion. Each of these methods is shown in Figure 8-8 through Figure 8-11 using the signal names and parameters given in Table 8-4. * * * * Manual start and stop (mode 0) Figure 8-8 Manual start and automatic discharge (mode 1) Figure 8-9 Automatic start and stop from TOF to ICF (mode 2) Figure 8-10 Automatic start and stop from OCF to ICF (mode 3) Figure 8-11
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Table 8-4. A/D Conversion Parameters
Name VX VMAX ICHG Function Unknown voltage on channel selection bus Maximum charging voltage on external capacitor Charging current on external ramping capacitor VDD = 3 Vdc VDD = 5 Vdc Discharge current on external ramping capacitor Time to charge external capacitor (100 kHz < fOSC < 4.0 MHz) 4-bit result 6-bit result 8-bit result 10-bit result 12-bit result Time to discharge external capacitor, CEXT Capacitance of external ramping capacitor Number of counts for ICHG to charge CEXT to VX Prescaler into timing function (/ P) Using core timer Using 16-bit programmable timer Using software loops Clock source frequency (excluding any prescaling) Min VSS -- Typ -- -- Max VDD -1.5 VDD -1.5 Units V V
Refer to 15.10 Analog Subsystem Characteristics (5.0 Vdc) and 15.11 Analog Subsystem Characteristics (3.0 Vdc) Refer to 15.10 Analog Subsystem Characteristics (5.0 Vdc) and 15.11 Analog Subsystem Characteristics (3.0 Vdc)
IDIS
tCHG
0.032 0.128 0.512 2.048 8.192 -- 0.0001 1 8 8 24
0.128 0.512 2.048 8.196 32.768 5 0.1 1024
2.56 10.24 40.96 120(1) 120(1) 10 2.0 65536
ms
tDIS CEXT N
ms/ F F Counts
P
8 8 8 8 User defined User defined
/P
fOSC
Refer to 15.12 Control Timing (5.0 Vdc) and 15.13 Control Timing (3.0 Vdc)
1. Limited by requirement for CEXT to be less than 2.0 F
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Table 8-5. Sample Conversion Timing (VDD = 5.0 Vdc)
Bits Counts VX (Vdc) A/D Method Software loop (12 bus cycles) (24 fOSC cycles) Mode 0 or 1 (manual) Programmable timer (prescaler = 8) Mode 2 or 3 (TOF ICF or OCF ICF) Software loop (12 bus cycles) (24 fOSC cycles) Mode 0 or 1 (manual) Programmable timer (prescaler = 8) Mode 2 or 3 (TOF CF or OCF ICF) Software loop (12 bus cycles) (24 fOSC cycles) Mode 0 or 1 (manual) Programmable timer (prescaler = 8) Mode 2 or 3 (TOF CF or OCF ICF) Programmable timer (prescaler = 8) Mode 2 or 3 (TOF ICF or OCF ICF) Programmable timer (prescaler = 8) Mode 2 or 3 (TOF ICF or OCF ICF) Clock Source Low-power oscillator External pin oscillator Low-power oscillator External pin oscillator Low-power oscillator External pin oscillator Low-power oscillator External pin oscillator Low-power oscillator External pin oscillator Low-power oscillator External pin oscillator Low-power oscillator External pin oscillator Low-power oscillator External pin oscillator fOSC (MHz) 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 tCHG (ms) 3.840 0.384 0.192 0.096 1.280 0.128 0.064 0.032 15.36 1.536 0.768 0.384 5.120 0.512 0.256 0.128 61.44 6.144 3.072 1.536 20.48 2.048 1.024 0.512 Note 1 8.192 4.096 2.048 Note 1 32.768 16.384 8.192 CEXT (F) 0.110 0.011 0.006 0.003 0.037 0.004 0.002 0.001 0.439 0.044 0.022 0.011 0.585 0.059 0.029 0.015 1.755 0.176 0.088 0.044 0.585 0.059 0.029 0.015 Note 1 0.234 0.117 0.059 Note 1 0.936 0.468 0.234
4
16
3.5
4
16
3.5
6
64
3.5
6
64
3.5
8
256
3.5
8
256
3.5
10
1024
3.5
12
4096
3.5
1. Not usable as the value of CEXT would be greater than 2.0 F
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tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tMAX tDIS (MIN) VMAX
CHG
COMP2
TOF
OCF
ICF
0 1
2
3
4
5
1
Point 0 1 2 3 4 5
Action Begin initial discharge and select mode 0 by clearing the CHG, ATD2, and ATD1 control bits in the ACR. VCAP falls to VSS. Stop discharge and begin charge by setting CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2. VCAP reaches VMAX. Begin next discharge by clearing the CHG control bit in the ACR. Reset CPF2 by writing a 1 to CPFR2.
Software/Hardware Action Software write Wait out minimum tDIS time. Software write Wait out tCHG time. None Software write
Dependent Variable(s) Software VMAX, IDIS, CEXT Software VX, ICHG, CEXT VMAX, ICHG, CEXT Software
Figure 8-8. A/D Conversion -- Full Manual Control (Mode 0)
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tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tDIS (MIN) VMAX
CHG
COMP2
TOF
OCF
ICF
0
1
2
3
1
2
Point 0 1 2
Action Begin initial discharge and select mode 1 by clearing CHG and ATD2 and setting ATD1 in the ACR. VCAP falls to VSS. Stop discharge and begin charge by setting CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2, which clears CHG control bit in the ACR. Reset CPF2 by writing a 1 to CPFR2.
Software/Hardware Action Software write Wait out minimum tDIS time. Software write
Dependent Variable(s) Software VMAX, IDIS, CEXT Software
3
Wait out tCHG time. CPF2 clears CHG control bit.
VX, ICHG, CEXT
Figure 8-9. A/D Conversion -- Manual/Auto Discharge Control (Mode 1)
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tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tDIS (MIN) VMAX
CHG
COMP2 (TCAP) TOF
OCF
ICF
0
1
2
3
1
2
Point
Action Begin initial discharge and select mode 2 by clearing CHG and ATD1 and setting ATD2 in the ACR. Also set ICEN bit in ACR and IEDG bit in TCR. VCAP falls to VSS. Stop discharge and begin charge when the next TOF sets the CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2, which causes an ICF from the timer and clears the CHG control bit in ACR. Must clear CPF2 to trap next CPF2 flag.
Software/Hardware Action
Dependent Variable(s)
0
Software write
Software
1 2
Wait out minimum tDIS time. Timer TOF sets the CHG control bit in the ACR.
VMAX, IDIS, CEXT Free-running timer counter overflow, fOSC
3
Wait out tCHG time. Timer ICF clears the CHG control bit in the ACR.
VX, ICHG, CEXT
Figure 8-10. A/D Conversion -- TOF/ICF Control (Mode 2)
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tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tDIS (MIN) VMAX
CHG
COMP2 (TCAP) TOF
OCF
ICF
0
1
2
3
1
2
Point 0
Action Begin initial discharge and select mode 3 by clearing CHG and setting ATD2 and ATD1 in the ACR. Also set ICEN bit in ACR and IEDG bit in TCR. VCAP falls to VSS. Set timer output compare registers (OCRH and OCRL) to desired charge start time. Stop discharge and begin charge when the next OCF sets the CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2, which causes an ICF from the timer and clears the CHG control bit in ACR. Must clear CPF2 to trap next CPF2 flag. Load next OCF.
Software/Hardware Action Software write
Dependent Variable(s) Software
1
Wait out minimum tDIS time. Software write to OCRH, OCRL Timer OCF sets the CHG control bit in the ACR.
VMAX, IDIS, CEXT, software Free-running timer output compare, fOSC
2
3
Wait out tCHG time. Timer ICF clears the CHG control bit in the ACR.
VX, ICHG, CEXT
Figure 8-11. A/D Conversion -- OCF/ICF Control (Mode 3)
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8.7 Voltage Measurement Methods
The methods for obtaining a voltage measurement can use software techniques to express these voltages as absolute or ratiometric readings. In most applications the external capacitor, the clock source, the reference voltage, and the charging current may vary between devices and with changes in supply voltage or ambient temperature. All of these variations must be considered when determining the desired resolution of the measurement. The maximum and minimum extremes for the full scale count will be: NFSMIN = CEXTMIN x VFSMIN x fOSCMIN / (P x ICHGMAX) NFSMAX = CEXTMAX x VFSMAX x fOSCMAX / (P x ICHGMIN) The minimum count should be the desired resolution, and the counting mechanism must be capable of counting to the maximum. The final scaling of the count will be by a math routine which calculates: VX = VREF x (NX - NOFF) / (NREF - NOFF) Where: VREF = Known reference voltage VX NX = Unknown voltage between VSS and VREF = Conversion count for unknown voltage
NREF = Conversion count for known reference voltage (VREF) NOFF = Conversion count for minimum reference voltage (VSS) When VREF is a stable voltage source such as a zener or other reference source, then the unknown voltage will be determined as an absolute reading. If VREF is the supply source to the device (VDD), then the unknown voltage will be determined as a ratio of VDD, or a ratiometric reading. If the unknown voltage applied to the comparator is greater than its common-mode range (VDD -1.5 volts), then the external capacitor will try to charge to the same level. This will cause both comparator inputs to be above the common-mode range and the output of the comparator will
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be indeterminate. In this case the comparator output flags may also be set even if the actual voltage on the positive input (+) is less than the voltage on the negative input (-). All A/D conversion methods should have a maximum time check to determine if this case is occurring. Once the maximum timeout detection has been made, the state of the comparator outputs can be tested to determine the situation. However, such tests should be carefully designed when using modes 1, 2, or 3 as these modes cause the immediate automatic discharge of the external ramping capacitor before any software check can be made of the output state of comparator 2.
NOTE:
All A/D conversion methods should include a test for a maximum elapsed time to detect error cases where the inputs may be outside of the design specification.
8.7.1 Absolute Voltage Readings The absolute value of a voltage measurement can be calculated in software by first taking a reference reading from a fixed source and then comparing subsequent unknown voltages to that reading as a percentage of the reference voltage multiplied times the known reference value. The accuracy of absolute readings will depend on the error sources taken into account using the features of the analog subsystem and appropriate software as described in Table 8-6. As can be seen from this table, most of the errors can be reduced by frequent comparisons to a known voltage, use of the inverted comparator inputs, and averaging of multiple samples. 8.7.1.1 Internal Absolute Reference If a stable source of VDD is provided, the reference measurement point can be internally selected. In this case, the reference reading can be taken by setting the VREF bit and clearing the MUX1:4 bits in the AMUX register. This connects the channel selection bus to the VDD pin. To stay within the VMAX range, the DHOLD bit should be used to select the 1/2 divided input.
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8.7.1.2 External Absolute Reference If a stable external source is provided, the reference measurement point can be any one of the channel selected pins from PB1-PB4. In this case the reference reading can be taken by setting the MUX bit in the AMUX which connects channel selection bus to the pin connected to the external reference source. If the external reference is greater than VDD -1.5 volts, then the DHOLD bit should be used to select the 1/2 divided input. Table 8-6. Absolute Voltage Reading Errors
Error Source Change in reference voltage Change in magnitude of ramp current source Non-linearity of ramp current source vs. voltage Frequency shift in internal low-power oscillator Sampling capacitor leakage Internal voltage divider ratio Input offset voltage of comparator 2 Noise internal to MCU Accuracy Improvements Possible In Hardware Provide closer tolerance reference Not adjustable In Software Calibration and storage of reference source over temperature and supply voltage Compare unknown with recent measurement from reference Calibration and storage of voltages at 1/4, 1/2, 3/4, and FS Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference OR avoid use of divided input Sum two readings on reference or unknown using INV and INV control bit and divide by 2 (average of both) Average multiple readings on both the reference and the unknown voltage
Not adjustable
Use external oscillator with crystal
Use faster conversion times
Not adjustable
Not adjustable Close decoupling at VDD and VSS pins and reduce supply source impedance
8.7.2 Ratiometric Voltage Readings The ratiometric value of a voltage measurement can be calculated in software by first taking a reference reading from a reference source and then comparing subsequent unknown voltages to that reading as a percentage of the reference value. The accuracy of ratiometric readings
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Analog Subsystem Voltage Measurement Methods
will depend on the variety of sources, but will generally be better than for absolute readings. Many of these error sources can be taken into account using the features of the analog subsystem and appropriate software as described in Table 8-7. As with absolute measurements, most of the errors can be reduced by frequent comparisons to the reference voltage, use of the inverted comparator inputs, and averaging of multiple samples. Table 8-7. Ratiometric Voltage Reading Errors
Error Source Change in reference voltage Change in magnitude of ramp current source Non-linearity of ramp current source vs. voltage Frequency shift in internal low-power oscillator Accuracy Improvements Possible In Hardware Not required for ratiometric Not adjustable Not adjustable Not required for ratiometric In Software Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Calibration and storage of voltages at 1/4, 1/2, 3/4, and FS Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Sum two readings on reference or unknown using INV and INV control bit and divide by 2 (average of both) Average multiple readings on both the reference and the unknown voltage
Sampling capacitor leakage Use faster conversion times Internal voltage divider ratio Not adjustable Input offset voltage of comparator 2 Noise internal to MCU
Not adjustable Close decoupling at VDD and VSS pins and reduce supply source impedance
8.7.2.1 Internal Ratiometric Reference If readings are to be ratiometric to VDD, the reference measurement point can be internally selected. In this case the reference reading can be taken by setting the VREF bit and clearing the MUX1:4 bits in the AMUX register which connects the channel selection bus to the VDD pin. In order to stay within the VMAX range, the DHOLD bit should be used to select the 1/2 divided input.
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8.7.2.2 External Ratiometric Reference If readings are to be ratiometric to some external source, the reference measurement point can be connected to any one of the channel selected pins from PB1-PB4. In this case, the reference reading can be taken by setting the MUX bit in the AMUX which connects channel selection bus to the pin connected to the external reference source. If the external reference is greater than VDD -1.5 volts, then the DHOLD bit should be used to select the 1/2 divided input.
8.8 Voltage Comparator Features
The two internal comparators can be used as simple voltage comparators if set up as described in Table 8-8. Both comparators can be active in the wait mode and can directly restart the part by means of the analog interrupt. Both comparators can also be active in the stop mode, but cannot directly restart the part. However, the comparators can directly drive PB4 which can then be connected externally to activate either a port interrupt on the PA0:3 pins or the IRQ/VPP pin. Table 8-8. Voltage Comparator Setup Conditions
Current Source Enable Not affected ISEN = 0 Discharge Device Disable Not affected ISEN = 0 Port B Pin as Inputs DDRB2 = 0 DDRB3 = 0 DDRB0 = 0 DDRB1 = 0 Port B Pin Pulldowns Disabled PDIB2 = 1 PDIB3 = 1 PDIB0 = 1 PDIB1 = 1 Prog. Timer Input Capture Source Not affected ICEN = 0 IEDG = 1
Comparator
1 2
8.8.1 Voltage Comparator 1 Voltage comparator 1 is always connected to two of the port B I/O pins. These pins should be configured as inputs and have their software programmable pulldowns disabled. Also, the negative input of voltage comparator 1 is connected to the PB3/AN3/TCAP and shared with the input capture function of the 16-bit programmable timer. Therefore, the timer input capture interrupt should be disabled so that changes in the
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voltage on the PB3/AN3/TCAP pin do not cause unwanted input capture interrupts. The output of comparator 1 can be connected to the port logic driving the PB4/AN4/TCMP/CMP1 pin such that the output of the comparator is ORed with the PB4 data bit and the OLVL bit from the 16-bit timer. This capability requires that the OPT bit is set in the COPR at location $1FF0 as in Figure 8-12, and the COE1 bit is set in the ASR at location $001E.
Address: $1FF0 Bit 7 Read: Write: Reset: EPMSEC U 6 OPT U U U U = Unaffected U U U 5 4 3 2 1 Bit 0
COPC U
= Unimplemented
Figure 8-12. COP and Security Register (COPR) OPT -- Optional Features Bit The OPT bit enables two additional features: direct drive by comparator 1 output to PB4 and voltage offset capability to sample capacitor in analog subsystem. 1 = Optional features enabled 0 = Optional features disabled
8.8.2 Voltage Comparator 2 Voltage comparator 2 can be used as a simple comparator if its charge current source and discharge device are disabled by clearing the ISEN bit in the ACR. If the ISEN bit is set, the internal ramp discharge device connected to PB0/AN0 may become active and try to pull down any voltage source that may be connected to that pin. Also, since voltage comparator 2 is always connected to two of the port B I/O pins, these pins should be configured as inputs and have their software programmable pulldowns disabled.
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8.9 Current Source Features
The internal current source connected to the PB0/AN0 pin supplies about 100 A of current when the discharge device is disabled and the current source is active. Therefore, this current source can be used in an application if the ISEN enable bit is set to power up the current source and by setting the A/D conversion method to manual mode 0 (ATD1 and ATD2 cleared) and the charge current enabled (CHG set).
8.10 Internal Temperature Sensing Diode Features
An internal diode is forward biased to VSS and will have its voltage change, VD, for each degree centigrade rise in the temperature of the device. This temperature sensing diode is powered up from a current source only during the time that the diode is selected. When on, this current source typically adds about 30 A to the IDD current. The temperature sensing diode can be selected by setting both the HOLD and DHOLD bits in the AMUX register (see 8.3 Analog Multiplex Register).
8.11 Sample and Hold
When using the internal sample capacitor to capture a voltage for later conversion, the HOLD or DHOLD bit must be cleared first before changing any channel selection. If both the HOLD (or DHOLD) bit and the channel selection are changed on the same write cycle, the sample may be corrupted during the switching transitions.
NOTE:
The sample capacitor can be affected by excessive noise created with respect to the device's VSS pin such that it may appear to leak down or charge up depending on the voltage level stored on the sample capacitor. It is recommended to avoid switching large currents through the port pins while a voltage is to remain stored on the sample capacitor. The additional option of adding an offset voltage to the bottom of the sample capacitor allows unknown voltages near VSS to be sampled and then shifted up past the comparator offset and the device offset caused
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Analog Subsystem Port B Interaction with Analog Inputs
by a single VSS return pin. This offset also provides a means to measure the internal VSS level regardless of the comparator offset to determine NOFF as described in 8.7 Voltage Measurement Methods. In either case the OPT bit must be set in the COPR located at $1FF0 as in Figure 8-12 and the VOFF bit must be set in the ASR. It is not necessary to switch the VOFF bit during conversions, since the offset is controlled by the HOLD and DHOLD bits when the VOFF is active. Refer to 8.3 Analog Multiplex Register for more details on the design and decoding of the sample and hold circuit.
8.12 Port B Interaction with Analog Inputs
The analog subsystem is connected directly to the port B I/O pins without any intervening gates. It is, therefore, possible to measure the voltages on port B pins set as inputs or to have the analog voltage measurements corrupted by port B pins set as outputs.
8.13 Port B Pins as Inputs
All the port B pins will power up as inputs or return to inputs after a reset of the device since the bits in the port B data direction register will be reset. If any port B pins are to be used for analog voltage measurements, they should be left as inputs. In this case, not only can the voltage on the pin be measured, but the logic state of the port B pins can be read from location $0002.
8.14 Port B Pulldowns
All the port B pins have internal software programmable pulldown devices available dependent on the state of the SWPDI bit in the mask option register (MOR). If the pulldowns are enabled, they will create an approximate 100 A load to any analog source connected to the pin. In some cases, the analog source may be able to supply this current without causing any
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error due to the analog source output impedance. Since this may not always be true, it is therefore best to disable port B pulldowns on those pins used for analog input sources.
8.15 Noise Sensitivity
In addition to the normal effects of electrical noise on the analog input signal there can also be other noise-related effects caused by the digital-to-analog interface. Since there is only one VSS return for both the digital and the analog subsystems on the device, currents in the digital section may affect the analog ground reference within the device. This can add voltage offsets to measured inputs or cause channel-to-channel crosstalk. To reduce the impact of these effects, there should be no switching of heavy I/O currents to or from the device while there is a critical analog conversion or voltage comparison in process. Limiting switched I/O currents to 2-4 mA during these times is recommended. A noise reduction benefit can be gained with 0.1-F bypass capacitors from each analog input (PB4:1) to the VSS pin. Also, try to keep all the digital power supply or load currents from passing through any conductors which are the return paths for an analog signal.
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Section 9. Simple Synchronous Serial Interface
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 9.4.1 SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . 145 9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.2 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial communications with peripheral devices or other MCUs. SIOP is implemented as a 3-wire master/slave system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block diagram of the SIOP is shown in Figure 9-1. The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in the SCR), the port B data direction and data registers are bypassed by the SIOP. The port B data direction and data registers will remain accessible and can be altered by the application software, but these actions will not affect the SIOP transmitted or received data.
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PORTB LOGIC OSCILLATOR CLOCK /2 SPR0 SPR1 SIOP CONTROL REGISTER (SCR) CPHA PORTB LOGIC MSTR SPE LSBF SPIR SPIE PORTB LOGIC $000A
INTERNAL M68HC05 BUS
CLOCK DIVIDER AND SELECT
CLOCK CONTROL PB7 SCK
PB6 SDI
DIN LATCH Q SPIF S R D0 D1 D2 D3 D4 D5 CLK COMP ERROR
DOUT 8-BIT SHIFT REGISTER PB5 SDO D6 SDR6 D7 SDR7
SIOP INTERRUPT
SIOP STATUS REGISTER (SSR)
DCOL
FORMAT CONTROL (LSB OR MSB FIRST)
SDR0
SDR1
SDR2
SDR3
SDR4
$000B
SIOP DATA REGISTER (SDR) $000C
INTERNAL M68HC05 BUS
Figure 9-1. SIOP Block Diagram
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SDR5
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Simple Synchronous Serial Interface SIOP Signal Format
9.3 SIOP Signal Format
The SIOP subsystem can be software configured for master or slave operation. No external mode selection inputs are available (for instance, no slave select pin).
9.3.1 Serial Clock (SCK) The state of the SCK output remains a fixed logic level during idle periods between data transfers. The edges of SCK indicate the beginning of each output data transfer and latch any incoming data received. The first bit of transmitted data is output from the SDO pin on the first falling edge of SCK. The first bit of received data is accepted at the SDI pin on the first rising edge of SCK after the first falling edge. The transfer is terminated upon the eighth rising edge of SCK. The idle state of the SCK is determined by the state of the CPHA bit in the SCR. When the CPHA is clear, SCK will remain idle at a logic 1 as shown in Figure 9-2. When the CPHA is set, SCK will remain idle at a logic 0 as shown in Figure 9-3. In both cases, the SDO changes data on the falling edge of the SCK, and the SDI latches data in on the rising edge of SCK.
BIT 1 SDO BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
SCK (CPHA = 0) 100 ns SDI BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 100 ns
(IDLE = 1)
Figure 9-2. SIOP Timing Diagram (CPHA = 0)
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BIT 1 SDO
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
SCK (CPHA = 1)
(IDLE = 0) 100 ns 100 ns
SDI BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
Figure 9-3. SIOP Timing Diagram (CPHA = 1) The only difference in the master and slave modes of operation is the sourcing of the SCK. In master mode, SCK is driven from an internal source within the MCU. In slave mode, SCK is driven from a source external to the MCU. The SCK frequency is based on one of four divisions of the oscillator clock that is selected by the SPR0 and SPR1 bits in the SCR.
9.3.2 Serial Data Input (SDI) The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New data is presented to the SDI pin on the falling edge of SCK. Valid data must be present at least 100 nanoseconds before the rising edge of SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
9.3.3 Serial Data Output (SDO) The SDO pin becomes an output as soon as the SIOP subsystem is enabled. The state of the PB5/SDO pin reflects the value of the first bit received on the previous transmission. Prior to enabling the SIOP, the PB5/SDO can be initialized to determine the beginning state. While SIOP is enabled, the port B logic cannot be used as a standard output since that pin is connected to the last stage of the SIOP serial shift register. A control bit (LSBF) is included in the SCR to allow the data to be transmitted in either the MSB first format or the LSB first format.
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Simple Synchronous Serial Interface SIOP Registers
The first data bit will be shifted out to the SDO pin on the first falling edge of the SCK. The remaining data bits will be shifted out to the SDI pin on subsequent falling edges of SCK. The SDO pin will present valid data at least 100 nanoseconds before the rising edge of the SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
9.4 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR) located at address $000A, the SIOP status register (SSR) located at address $000B, and the SIOP data register (SDR) located at address $000C.
9.4.1 SIOP Control Register (SCR) The SIOP control register (SCR) is located at address $000A and contains seven control bits and a write-only reset of the interrupt flag. Figure 9-4 shows the position of each bit in the register and indicates the value of each bit after reset.
Address: $000A Bit 7 Read: SPIE Write: Reset: 0 0 0 0 SPE LSBF MSTR SPIR 0 0 0 0 6 5 4 3 0 CPHA SPR1 SPR0 2 1 Bit 0
Figure 9-4. SIOP Control Register (SCR) SPIE -- Serial Peripheral Interrupt Enable Bit The SPIE bit enables the SIOP to generate an interrupt whenever the SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the state of the SPIF flag bit and will not terminate a serial interrupt once the interrupt sequence has started. Reset clears the SPIE bit. 1 = Serial interrupt enabled 0 = Serial interrupt disabled
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NOTE:
If the SPIE bit is cleared just after the serial interrupt sequence has started (for instance, the CPU status is being stacked), then the CPU will be unable to determine the source of the interrupt and will vector to the reset vector as a default. SPE -- Serial Peripheral Enable Bit The SPE bit switches the port B interface such that SDO/PB5 is the serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock output in the master mode. The port B DDR and data registers can be manipulated as usual, but these actions will not affect the transmitted or received data. The SPE bit is readable and writable at any time, but clearing the SPE bit while a transmission is in progress will 1) abort the transmission, 2) reset the serial bit counter, and 3) convert port B to a general-purpose I/O port. Reset clears the SPE bit. 1 = Serial peripheral enabled (port B I/O disabled) 0 = Serial peripheral disabled (port B I/O enabled) LSBF -- Least Significant Bit First Bit The LSBF bit controls the format of the transmitted and received data to be transferred LSB or MSB first. Reset clears this bit. 1 = LSB transferred first 0 = MSB transferred first MSTR -- Master Mode Select Bit The MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon the divider of the oscillator frequency selected by the SPR0:1 bits. When the device is in master mode, the SDO and SDI pins do not change function. These pins behave exactly the same in both the master and slave modes. The MSTR bit is readable and writable at any time regardless of the state of the SPE bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave mode. 1 = SIOP set up as master, SCK is an output 0 = SIOP set up as slave, SCK is an input
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Simple Synchronous Serial Interface SIOP Registers
SPIR -- Serial Peripheral Interrupt Reset Bit The SPIR bit is a write-only control to reset the SPIF flag bit in the SSR. Reading the SPIR bit will return a logic 0. 1 = Reset the SPIF flag bit 0 = No effect CPHA -- Clock Phase Bit The CPHA bit controls the clock timing and phase in the SIOP. Data is changed on the falling edge of SCK and data is captured (read) on the rising edge of SCK. This bit is cleared by reset. 1 = SCK is idle low 0 = SCK is idle high SPR0:1 -- Serial Peripheral Clock Rate Select Bits The SPR0 and SPR1 bits select one of four clock rates given in Table 9-1 to be supplied on the PB7/SCK pin when the device is configured with the SIOP as a master (MSTR = 1). The fastest rate is when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared by reset, which places the SIOP clock selection at the slowest rate. Table 9-1. SIOP Clock Rate Selection
SPR1 0 0 1 1 SPR0 0 1 0 1 SIOP Clock Rate Oscillator Frequency Divided by: 64 32 16 8
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9.4.2 SIOP Status Register The SIOP status register (SSR) is located at address $000B and contains two read-only bits. Figure 9-5 shows the position of each bit in the register and indicates the value of each bit after reset.
Address: $000B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 SPIF 6 DCOL 5 0 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 9-5. SIOP Status Register (SSR) SPIF -- Serial Port Interrupt Flag The SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data transfer has been completed. It has no effect on any future data transfers and can be ignored. The SPIF bit can be cleared by reading the SSR followed by a read or write of the SDR or by writing a logic 1 to the SPIR bit in the SCR. If the SPIF is cleared before the last rising edge of SCK it will be set again on the last rising edge of SCK. Reset clears the SPIF bit. 1 = Serial transfer complete, serial interrupt if the SPIE bit in SCR is set 0 = Serial transfer in progress or serial interface idle DCOL -- Data Collision Bit The DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF is set. Reading or writing the SDR during this time will result in invalid data being transmitted or received. The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or write of the SDR. If the last part of the clearing sequence is
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Simple Synchronous Serial Interface SIOP Registers
done after another transfer has started, the DCOL bit will be set again. Reset clears the DCOL bit. 1 = Illegal access of the SDR occurred 0 = No illegal access of the SDR detected
9.4.3 SIOP Data Register The SIOP data register (SDR) is located at address $000C and serves as both the transmit and receive data register. Writing to this register will initiate a message transmission if the node is in master mode. The SIOP subsystem is not double buffered and any write to this register will destroy the previous contents. The SDR can be read at any time. However, if a transfer is in progress the results may be ambiguous. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted and/or received. Figure 9-6 shows the position of each bit in the register. This register is not affected by reset.
Address: $000C Bit 7 Read: Bit 7 Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 9-6. SIOP Data Register (SDR)
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Section 10. Core Timer
10.1 Contents
10.2 10.3 10.4 10.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Core Timer Status and Control Register. . . . . . . . . . . . . . . . . 153 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . 155 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.2 Introduction
This section describes the operation of the core timer and the computer operating properly (COP) watchdog as shown by the block diagram in Figure 10-1.
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Core Timer
RESET INTERNAL CLOCK OVERFLOW $0009 CORE TIMER COUNTER REGISTER BITS 0-7 OF 15-STAGE RIPPLE COUNTER /4 /2 OSC1
INTERNAL CLOCK / 1024
INTERNAL DATA BUS
CORE TIMER INTERRUPT REQUEST
CTOFR
CTOFE
RTIFR
CTOF
RTIE
RTIF
$0008 RESET
CORE TIMER STATUS/CONTROL REGISTER RT1 RTI RATE SELECT $1FF0 COPR REGISTER /2 COPC /2 /2 /2 /2 /2 RT0
/2 POWER-ON RESET
/2
/2
/2
/2
COP WATCHDOG RESET
RESET
Figure 10-1. Core Timer Block Diagram
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Core Timer Core Timer Status and Control Register
10.3 Core Timer Status and Control Register
The read/write core timer status and control register (CTSCR) contains the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and the rate selects for the real-time interrupt as shown in Figure 10-2.
Address: $0008 Bit 7 Read: Write: Reset: 0 0 0 0 CTOF 6 RTIF CTOFE RTIE CTOFR 0 RTIFR 0 1 1 5 4 3 0 2 0 RT1 RT0 1 Bit 0
= Unimplemented
Figure 10-2. Core Timer Status and Control Register (CTSCR) CTOF -- Core Timer Overflow Flag This read-only flag becomes set when the first eight stages of the core timer counter roll over from $FF to $00. The CTOF flag bit generates a timer overflow interrupt request if CTOFE is also set. The CTOF flag bit is cleared by writing a logic 1 to the CTOFR bit. Writing to CTOF has no effect. Reset clears CTOF. 1 = Overflow in core timer has occurred. 0 = No overflow of core timer since CTOF last cleared RTIF -- Real-Time Interrupt Flag This read-only flag becomes set when the selected real-time interrupt (RTI) output becomes active. RTIF generates a real-time interrupt request if RTIE is also set. The RTIF enable bit is cleared by writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF. 1 = Overflow in real-time counter has occurred. 0 = No overflow of real-time counter since RTIF last cleared
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Core Timer
CTOFE -- Core Timer Overflow Interrupt Enable Bit This read/write bit enables core timer overflow interrupts. Reset clears CTOFE. 1 = Core timer overflow interrupts enabled 0 = Core timer overflow interrupts disabled RTIE -- Real-Time Interrupt Enable Bit This read/write bit enables real-time interrupts. Reset clears RTIE. 1 = Real-time interrupts enabled 0 = Real-time interrupts disabled CTOFR -- Core Timer Overflow Flag Reset Bit Writing a logic 1 to this write-only bit clears the CTOF bit. CTOFR always reads as a logic 0. Reset does not affect CTOFR. 1 = Clear CTOF flag bit 0 = No effect on CTOF flag bit RTIFR -- Real-Time Interrupt Flag Reset Bit Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads as a logic 0. Reset does not affect RTIFR. 1 = Clear RTIF flag bit 0 = No effect on RTIF flag bit RT1 and RT0 -- Real-Time Interrupt Select Bits 1 and 0 These read/write bits select one of four real-time interrupt rates, as shown in Table 10-1. Because the selected RTI output drives the COP watchdog, changing the real -time interrupt rate also changes the counting rate of the COP watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout period and longest real-time interrupt period.
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may cause a real-time interrupt request to be missed or an additional real-time interrupt request to be generated. Clear the COP timer just before changing RT1 and RT0.
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Core Timer Core Timer Counter Register
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow Interrupt Period TOF = 1/(fOSC / 211) (Microseconds) @ fOSC (MHz) 4.2 MHz 2.0 MHz 1.0 MHz Real-Time Interrupt Period (RTI) (Milliseconds) @ fOSC (MHz) 4.2 MHz 7.80 15.6 31.2 62.4 2.0 MHz 16.4 32.8 65.5 131 1.0 MHz 32.8 65.5 131 262 4.2 MHz Min 54.6 109 218 437 Max 62.4 125 250 499 COP Timeout Period COP = 7-to-8 RTI Periods (Milliseconds) @ fOSC (MHz) 2.0 MHz Min 115 229 459 918 Max 131 262 524 1049 1.0 MHz Min 229 459 918 1835 Max 262 524 1049 2097
RTI Rate RT1 RT0 = fOSC divided by:
0 0 488 1024 2048 1 1
0 1 0 1
215 216 217 218
10.4 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the basis of the core timer. The value of the first eight stages is readable at any time from the read-only timer counter register as shown in Figure 10-3.
Address: $0009 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR) Power-on clears the entire counter chain and begins clocking the counter. After the startup delay (16 or 4064 internal bus cycles depending on the DELAY bit in the mask option register (MOR)), the power-on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset.
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Each count of the timer counter register takes eight oscillator cycles or four cycles of the internal bus. A timer overflow function at the eighth counter stage allows a timer interrupt every 2048 oscillator clock cycles or every 1024 internal bus cycles.
10.5 COP Watchdog
Four counter stages at the end of the core timer make up the computer operating properly (COP) watchdog which can be enabled by the COPEN bit in the MOR. The COP watchdog is a software error detection system that automatically times out and resets the MCU if the COP watchdog is not cleared periodically by a program sequence. Writing a logic 0 to COPC bit in the COPR register clears the COP watchdog and prevents a COP reset.
Address: $1FF0 Bit 7 Read: OPT Write: Reset: = Unimplemented EPMSEC Unaffected by reset COPC 6 5 4 3 2 1 Bit 0
Figure 10-4. COP and Security Register (COPR) EPMSEC -- EPROM Security(1) Bit The EPMSEC bit is a write-only security bit to protect the contents of the user EPROM code stored in locations $0700-$1FFF. OPT -- Optional Features Bit The OPT bit enables two additional features: direct drive by comparator outputs to port A and voltage offset capability to sample capacitor in analog subsystem. 1 = Optional features enabled 0 = Optional features disabled
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users.
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Core Timer COP Watchdog
COPC -- COP Clear Bit This write-only bit resets the COP watchdog. The COP watchdog is active in the run, wait, and halt modes of operation if the COP is enabled by setting the COPEN bit in the MOR. The STOP instruction disables the COP watchdog by clearing the counter and turning off its clock source. In applications that depend on the COP watchdog, the STOP instruction can be disabled by setting the SWAIT bit in the MOR. In applications that have wait cycles longer than the COP timeout period, the COP watchdog can be disabled by clearing the COPEN bit. Table 10-2 summarizes recommended conditions for enabling and disabling the COP watchdog.
NOTE:
If the voltage on the IRQ/VPP pin exceeds 1.5 x VDD, the COP watchdog turns off and remains off until the IRQ/VPP pin voltage falls below 1.5 x VDD.
Table 10-2. COP Watchdog Recommendations
Voltage on IRQ/VPP Pin Less than 1.5 x VDD Less than 1.5 x VDD Less than 1.5 x VDD More than 1.5 x VDD SWAIT (in MOR)(1) 1 1 0 X Wait/Halt Time Less than COP timeout period Greater than COP timeout period X(3) X(3) Recommended COP Watchdog Condition Enabled(2) Disabled Disabled Disabled
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions. 2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction. 3. Don't care
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Section 11. Programmable Timer
11.1 Contents
11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Alternate Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Timer Operation during Wait Mode. . . . . . . . . . . . . . . . . . . . . 173
11.10 Timer Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . 173 11.11 Timer Operation during Halt Mode . . . . . . . . . . . . . . . . . . . . . 173
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11.2 Introduction
The MC68HC705JJ7/MC68HC705JP7 MCU contains a 16-bit programmable timer with an input capture function and an output compare function as shown by the block diagram in Figure 11-1. The basis of the capture/compare timer is a 16-bit free-running counter which increases in count with every four internal bus clock cycles. The counter is the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affecting the counter sequence. The input/output (I/O) registers for the input capture and output compare functions are pairs of 8-bit registers, because of the 16-bit timer architecture used. Each register pair contains the high and low bytes of that function. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. Because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles (every 524,288 oscillator clock cycles). Timer resolution with a 4-MHz crystal oscillator is 2 microseconds/count. The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012, and the status of the interrupt flags can be read from the timer status register (TSR) located at $0013.
Advance Information 160 Programmable Timer
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Programmable Timer Introduction
PB3 AN3 TCAP
INPUT SELECT MUX
EDGE SELECT & DETECT LOGIC ICF
ICRH ($0014)
ICRL ($0015)
CPF2 FLAG BIT FROM ANALOG SUBSYSTEM
TMRH ($0018) IEDG
TMRL ($0019)
ACRH ($001A)
ACRL ($001B)
ICEN CONTROL BIT OVERFLOW (TOF)
16-BIT COUNTER
/4
INTERNAL CLOCK (OSC / 2) PB4 AN4 TCMP
16-BIT COMPARATOR DQ OCRH ($0016) OCRL ($0017) C PIN I/O LOGIC
OLVL
OCF
ANALOG COMP 1
TIMER INTERRUPT REQUEST RESET IEDG OLVL OCIE TOIE OCF TOF ICIE ICF
TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS
TIMER STATUS REGISTER $0013
Figure 11-1. Programmable Timer Overall Block Diagram
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Programmable Timer
11.3 Timer Registers
The functional block diagram of the 16-bit free-running timer counter and timer registers is shown in Figure 11-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
LATCH READ TMRH RESET READ $FFFC
TMRL ($0019) TMR LSB /4
READ TMRL
TMRH ($0018) 16-BIT COUNTER OVERFLOW (TOF)
INTERNAL CLOCK (OSC / 2) TIMER INTERRUPT REQUEST
TOIE
TIMER CONTROL REG. $0012
TIMER STATUS REG. $0013 INTERNAL DATA BUS
Figure 11-2. Programmable Timer Block Diagram The timer registers (TMRH and TMRL) shown in Figure 11-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. The TMRL latch is a transparent read of the LSB until a read of the TMRH takes place. A read of the TMRH latches the LSB into the TMRL location until the TMRL is again read. The latched value remains fixed even if multiple reads of the TMRH take place before the next read of the TMRL. Therefore, when reading the MSB of the timer at TMRH, the LSB of the timer at TMRL must also be read to complete the read sequence. During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles).
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TOF
Programmable Timer Alternate Counter Registers
Address:
$0018 Bit 7 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Read: Write: Reset: Address:
Bit 15
1 $0018 Bit 7
1
1
1
1
1
1
1
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
Read: Write: Reset:
Bit 7
1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-3. Programmable Timer Registers (TMRH and TMRL)
When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR. Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of times does not have any effect on the 16-bit free-running counter.
NOTE:
To prevent interrupts from occurring between readings of the TMRH and TMRL, set the I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL.
11.4 Alternate Counter Registers
The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 11-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF
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Programmable Timer
flag bit and timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL DATA BUS LATCH ACRL ($001B) READ ACRL
READ ACRH RESET
READ $FFFC
ACRH ($001A)
TMR LSB /4 INTERNAL CLOCK (OSC / 2)
16-BIT COUNTER
Figure 11-4. Alternate Counter Block Diagram The alternate counter registers (ACRH and ACRL) shown in Figure 11-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the device presets the timer counter to $FFFC. The ACRL latch is a transparent read of the LSB until a read of the ACRH takes place. A read of the ACRH latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the MSB of the timer at ACRH, the LSB of the timer at ACRL must also be read to complete the read sequence. During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit free-running counter or the TOF flag bit.
NOTE:
To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL.
Advance Information 164 Programmable Timer
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Programmable Timer Input Capture Registers
Address:
$001A Bit 7 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Read: Write: Reset: Address:
Bit 15
1 $001B Bit 7
1
1
1
1
1
1
1
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
Read: Write: Reset:
Bit 7
1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-5. Alternate Counter Registers (ACRH and ACRL)
11.5 Input Capture Registers
The input capture function is a means to record the time at which an event occurs. The source of the event can be the change on an external pin (PB3/AN3/TCAP) or the CPF2 flag bit of voltage comparator 2 in the analog subsystem. The ICEN bit in the analog subsystem control register (ACR) at $001D selects which source is the input signal. When the input capture circuitry detects an active edge on the selected source, it latches the contents of the free-running timer counter registers into the input capture registers as shown in Figure 11-6.
NOTE:
Both the ICEN bit in the ACR and the IEDG bit in the TCR must be set when using voltage comparator 2 to trigger the input capture function. Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Programmable Timer
Advance Information 165
Programmable Timer
READ ICRH PB3 AN3 TCAP CPF2 FLAG BIT FROM ANALOG SUBSYSTEM ICEN CONTROL BIT RESET INPUT SELECT MUX EDGE SELECT & DETECT LOGIC $FFFC IEDG LATCH ICRH ($0014) ICRL ($0015)
INTERNAL DATA BUS
READ ICRL /4 INTERNAL CLOCK (OSC / 2) TIMER INTERRUPT REQUEST
16-BIT COUNTER INPUT CAPTURE (ICF)
IEDG
ICIE
TIMER CONTROL REG. $0012
ICF TIMER STATUS REG. $0013 INTERNAL DATA BUS
Figure 11-6. Timer Input Capture Block Diagram The input capture registers are made up of two 8-bit read-only registers (ICRH and ICRL) as shown in Figure 11-7. The input capture edge detector contains a Schmitt trigger to improve noise immunity. The edge that triggers the counter transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not affect the contents of the input capture registers.
Address: $0014 Bit 7 Read: Write: Reset: Address: $0015 Bit 7 Read: Write: Reset: = Unimplemented Unaffected by reset Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Unaffected by reset Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Figure 11-7. Input Capture Registers (ICRH and ICRL)
Advance Information 166 Programmable Timer MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Programmable Timer Output Compare Registers
The result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles). Reading the ICRH inhibits future captures until the ICRL is also read. Reading the ICRL after reading the timer status register (TSR) clears the ICF flag bit. There is no conflict between reading the ICRL and transfers from the free-running timer counters. The input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture.
NOTE:
To prevent interrupts from occurring between readings of the ICRH and ICRL, set the I bit in the condition code register (CCR) before reading ICRH and clear the I bit after reading ICRL.
11.6 Output Compare Registers
The output compare function is a means of generating an output signal when the 16-bit timer counter reaches a selected value as shown in Figure 11-8. Software writes the selected value into the output compare registers. On every fourth internal clock cycle (every eight oscillator clock cycles) the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. When a match occurs, the timer transfers the output level (OLVL) from the timer control register (TCR) to the PB4/AN4/TCMP pin. Software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the PB4/AN4/TCMP pin. The planned action on the PB4/AN4/TCMP pin depends on the value stored in the OLVL bit in the TCR, and it occurs when the value of the 16-bit free-running timer counter matches the value in the output compare registers shown in Figure 11-9. These registers are read/write bits and are unaffected by reset.
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Advance Information 167
Programmable Timer
R/W OCRH
OCRH ($0016)
OCRL ($0017) EDGE SELECT DETECT LOGIC /4
R/W OCRL PB4 AN4 TCMP INTERNAL CLOCK (OSC / 2) TIMER INTERRUPT REQUEST
16-BIT COMPARATOR OLVL 16-BIT COUNTER OUTPUT COMPARE (OCF) OLVL TIMER CONTROL REG. $0012 OCF TIMER STATUS REG. $0013
$FFFC
RESET
OCIE
INTERNAL DATA BUS
Figure 11-8. Timer Output Compare Block Diagram
Address:
$0016 Bit 7 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Read: Bit 15 Write: Reset: Address: $0017 Bit 7 Read: Bit 7 Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 Unaffected by reset
Figure 11-9. Output Compare Registers (OCRH and OCRL)
Advance Information 168 Programmable Timer
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Programmable Timer Output Compare Registers
Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TCR will clear the output compare flag bit (OCF). The output compare OLVL state will be clocked to its output latch regardless of the state of the OCF. To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. Disable interrupts by setting the I bit in the condition code register. 2. Write to the OCRH. Compares are now inhibited until OCRL is written. 3. Read the TSR to arm the OCF for clearing. 4. Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in the TSR. 5. Enable interrupts by clearing the I bit in the condition code register. A software example of this procedure is shown in Table 11-1. Table 11-1. Output Compare Initialization Example
9B ... ... B7 B6 BF ... ... 9A SEI ... ... STA LDA STX ... ... CLI DISABLE INTERRUPTS ..... ..... INHIBIT OUTPUT COMPARE ARM OCF FLAG FOR CLEARING READY FOR NEXT COMPARE, OCF CLEARED ..... ..... ENABLE INTERRUPTS
16 13 17
OCRH TSR OCRL
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Programmable Timer
11.7 Timer Control Register
The timer control register (TCR) shown in Figure 11-10, performs the following functions: * * * * * Enables input capture interrupts Enables output compare interrupts Enables timer overflow interrupts Controls the active edge polarity of the TCAP signal Controls the active level of the TCMP output
Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected.
Address: $0012 Bit 7 Read: ICIE Write: Reset: 0 0 0 0 0 U = Unaffected 0 U 0 OCIE TOIE 6 5 4 0 3 0 2 0 IEDG OLVL 1 Bit 0
= Unimplemented
Figure 11-10. Timer Control Register (TCR) ICIE -- Input Capture Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCAP pin or from CPF2 flag bit of the analog subsystem voltage comparator 2. Reset clears the ICIE bit. 1 = Input capture interrupts enabled 0 = Input capture interrupts disabled OCIE -- Output Compare Interrupt Enable Bit This read/write bit enables interrupts caused by an active match of the output compare function. Reset clears the OCIE bit. 1 = Output compare interrupts enabled 0 = Output compare interrupts disabled
Advance Information 170 Programmable Timer
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Programmable Timer Timer Status Register
TOIE -- Timer Overflow Interrupt Enable This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled IEDG -- Input Capture Edge Select The state of this read/write bit determines whether a positive or negative transition triggers a transfer of the contents of the timer register to the input capture register. This transfer can occur due to transitions on the TCAP pin or the CPF2 flag bit of voltage comparator 2. Resets have no effect on the IEDG bit. 1 = Positive edge (low-to-high transition) triggers input capture 0 = Negative edge (high-to-low transition) triggers input capture
NOTE:
The IEDG bit must be set when either mode 2 or 3 of the analog subsystem is being used for A/D conversions. Otherwise, the input capture will not occur on the rising edge of the comparator 2 flag. OLVL -- Output Compare Output Level Select The state of this read/write bit determines whether a logic 1 or a logic 0 is transferred to the TCMP pin when a successful output compare occurs. Reset clears the OLVL bit. 1 = Signal to TCMP pin goes high on output compare. 0 = Signal to TCMP pin goes low on output compare.
11.8 Timer Status Register
The timer status register (TSR) shown in Figure 11-11 contains flags for these events: * An active signal on the TCAP pin or the CPF2 flag bit of voltage comparator 2 in the analog subsystem, transferring the contents of the timer registers to the input capture registers A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to the PB4/AN4/TCMP pin if that pin is set as an output An overflow of the timer registers from $FFFF to $0000
Advance Information Programmable Timer 171
*
*
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Programmable Timer
Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits in the TSR.
Address: $0013 Bit 7 Read: Write: Reset: U U U 0 0 U = Unaffected 0 0 0 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 11-11. Timer Status Register (TSR) ICF -- Input Capture Flag The ICF bit is automatically set when an edge of the selected polarity occurs on the TCAP pin. Clear the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL, $0015) of the input capture registers. Resets have no effect on ICF. OCF -- Output Compare Flag The OCF bit is automatically set when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with the OCF set and then accessing the low byte (OCRL, $0017) of the output compare registers. Resets have no effect on OCF. TOF -- Timer Overflow Flag The TOF bit is automatically set when the 16-bit timer counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with the TOF set and then accessing the low byte (TMRL, $0019) of the timer registers. Resets have no effect on TOF.
Advance Information 172 Programmable Timer
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Programmable Timer Timer Operation during Wait Mode
11.9 Timer Operation during Wait Mode
During wait mode, the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of wait mode.
11.10 Timer Operation during Stop Mode
When the MCU enters stop mode, the free-running counter stops counting (the internal processor clock is stopped). It remains at that particular count value until stop mode is exited by applying a low signal to the IRQ/VPP pin, at which time the counter resumes from its stopped value as if nothing had happened. If stop mode is exited via an external reset (logic low applied to the RESET pin), the counter is forced to $FFFC. If a valid input capture edge occurs during stop mode, the input capture detect circuitry will be armed. This action does not set any flags or wake up the MCU, but when the MCU does wake up there will be an active input capture flag (and data) from the first valid edge. If the stop mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during stop mode.
11.11 Timer Operation during Halt Mode
When the MCU enters halt mode, the functions and states of the 16-bit programmable timer are the same as for wait mode described in 11.9 Timer Operation during Wait Mode.
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Advance Information 173
Programmable Timer
Advance Information 174 Programmable Timer
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Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 12. Personality EPROM (PEPROM)
12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.3.1 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . 177 12.3.2 PEPROM Status and Control Register. . . . . . . . . . . . . . . . 178 12.4 12.5 12.6 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 PEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
12.2 Introduction
This section describes how to program the 64-bit personality erasable programmable read-only memory (PEPROM). Figure 12-1 shows the structure of the PEPROM subsystem.
NOTE:
In packages with no quartz window, the PEPROM functions as one-time programmable ROM (OTPROM).
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Personality EPROM (PEPROM)
Advance Information 175
Personality EPROM (PEPROM)
INTERNAL DATA BUS $000F PEPROM STATUS/CONTROL REGISTER 0 0 0 0 0 RESET
PEPGM
SINGLE SENSE AMPLIFIER
VPP
COL 0
COL 1
COL 2
COL 3
COL 4
COL 5
COL 6
VPP SWITCH
8-TO-1 COLUMN DECODER AND MULTIPLEXER
COL 7
PEPRZF ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7
PEDATA
8-TO-1 ROW DECODER AND MULTIPLEXER
VPP SWITCH
ROW ZERO DECODER PEB5 PEB4 PEB3 PEB2 PEB1 PEB0 0 0
PEPROM BIT SELECT REGISTER $000E INTERNAL DATA BUS
RESET
Figure 12-1. Personality EPROM Block Diagram
Advance Information 176
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Personality EPROM (PEPROM) MOTOROLA
Personality EPROM (PEPROM) PEPROM Registers
12.3 PEPROM Registers
Two I/O registers control programming and reading of the PEPROM: * * The PEPROM bit select register (PEBSR) The PEPROM status and control register (PESCR)
12.3.1 PEPROM Bit Select Register The PEPROM bit select register (PEBSR) selects one of 64 bits in the PEPROM array. Reset clears all the bits in the PEPROM bit select register.
Address: $000E Bit 7 Read: PEB7 Write: Reset: 0 0 0 0 0 0 0 0 PEB6 PEB5 PEB4 PEB3 PEB2 PEB1 PEB0 6 5 4 3 2 1 Bit 0
Figure 12-2. PEPROM Bit Select Register (PEBSR) PEB7 and PEB6 -- Not connected to the PEPROM array These read/write bits are available as storage locations. Reset clears PEB7 and PEB6. PEB5-PEB0 -- PEPROM Bit Selects These read/write bits select one of 64 bits in the PEPROM as shown in Table 12-1. Bits PEB2-0 select the PEPROM row, and bits PEB5-PEB3 select the PEPROM column. Reset clears PEB5-PEB0, selecting the PEPROM bit in row zero, column zero.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Personality EPROM (PEPROM)
Advance Information 177
Personality EPROM (PEPROM)
12.3.2 PEPROM Status and Control Register The PEPROM status and control register (PESCR) controls the PEPROM programming voltage. This register also transfers the PEPROM bits to the internal data bus and contains a flag bit when row zero is selected.
Address: $000F Bit 7 Read: Write: Reset: U 0 0 0 R PEDATA 6 0 PEPGM R 0 = Reserved R 0 R 0 U = Unaffected 1 5 4 0 3 0 2 0 1 0 Bit 0 PEPRZF
= Unimplemented
Figure 12-3. PEPROM Status and Control Register (PESCR) PEDATA -- PEPROM Data Bit This read-only bit is the output state of the PEPROM sense amplifier and shows the state of the currently selected bit. The state of the PEDATA bit does not affect the programming of the bit selected by the PEBSR. Reset does not affect the PEDATA bit. 1 = PEPROM data is a logic 1. 0 = PEPROM data is a logic 0. PEPGM -- PEPROM Program Control Bit This read/write bit controls the switches that apply the programming voltage from the IRQ/VPP pin to the selected PEPROM bit cell. When the PEPGM bit is set, the selected bit cell will be programmed to a logic 1, regardless of the state of the PEDATA bit. Reset clears the PEPGM bit. 1 = Programming voltage applied to array bit 0 = Programming voltage not applied to array bit PEPRZF -- PEPROM Row Zero Flag This read-only bit is set when the PEPROM bit select register selects the first row (row zero) of the PEPROM array. Selecting any other row clears PEPRZF. Monitoring PEPRZF can reduce the code needed to
Advance Information 178 MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Personality EPROM (PEPROM) MOTOROLA
Personality EPROM (PEPROM) PEPROM Programming
access one byte of eight PEPROM locations. Reset clears the PEPROM bit select register, thereby setting the PEPRZF bit by default. 1 = Row zero selected 0 = Row zero not selected Table 12-1. PEPROM Bit Selection
PEBSR $00 $01 | V $07 $08 $09 | V $37 $38 $39 | V $3E $3F PEPROM Bit Selected Row 0 Row 1 | V Row 7 Row 0 Row 1 | V Row 7 Row 0 Row 1 | V Row 6 Row 7 Column 0 Column 0 | V Column 0 Column 1 Column 1 | V Column 6 Column 7 Column 7 | V Column 7 Column 7
12.4 PEPROM Programming
Factory-provided software for programming the PEPROM is available on the World Wide Web at: http://www.motorola.com/mcu/
NOTE:
While the PEPGM bit is set and the VPP voltage level is applied to the IRQ/VPP pin, do not access bits that are to be left unprogrammed (erased). To program the PEPROM bits properly, the VDD voltage must be greater than 4.5 Vdc.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Personality EPROM (PEPROM)
Advance Information 179
Personality EPROM (PEPROM)
The PEPROM can also be programmed by user software with the VPP voltage level applied to the IRQ/VPP pin. This sequence shows how to program each PEPROM bit: 1. Select a PEPROM bit by writing to the PEBSR. 2. Set the PEPGM bit in the PESCR. 3. Wait for the programming time, tEPGM. 4. Clear the PEPGM bit. 5. Move to next PEPROM bit to be programmed in step 1.
12.5 PEPROM Reading
This sequence shows how to read the PEPROM: 1. Select a bit by writing to the PEBSR. 2. Read the PEDATA bit in the PESCR. 3. Store the PEDATA bit in RAM or in a register. 4. Select another bit by changing the PEBSR. 5. Continue reading and storing the PEDATA bits until the required personality EPROM data is retrieved and stored. Reading the PEPROM is easiest when each PEPROM column contains one byte. Selecting a row 0 bit selects the first bit, and incrementing the PEPROM bit select register (PEBSR) selects the next bit in row 1 from the same column. Incrementing PEBSR seven more times selects the remaining bits of the column and ends up selecting the bit in row 0 of the next column, thereby setting the row 0 flag, PEPRZF.
NOTE:
A PEPROM byte that has been read can be transferred to the personality EPROM bit select register (PEBSR) as a temporary storage location such that subsequent reads of the PEBSR quickly yield that PEPROM byte.
Advance Information 180
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Personality EPROM (PEPROM) MOTOROLA
Personality EPROM (PEPROM) PEPROM Erasing
12.6 PEPROM Erasing
MCUs with windowed packages permit PEPROM erasing with ultraviolet light. Erase the PEPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of a PEPROM bit is a logic 0.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Personality EPROM (PEPROM)
Advance Information 181
Personality EPROM (PEPROM)
Advance Information 182
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Personality EPROM (PEPROM) MOTOROLA
Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 13. EPROM/OTPROM
13.1 Contents
13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
13.3 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 13.3.1 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . 184 13.3.2 Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 13.3.3 EPROM Security Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.4 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.1 MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.2 EPMSEC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.5 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.2 Introduction
This section describes how to program the 6160-byte erasable programmable read-only memory/one-time programmable read-only memory (EPROM/OTPROM), the mask option register (MOR), and the EPROM security bit (EPMSEC).
NOTE:
In packages with no quartz window, the EPROM functions as one-time programmable ROM (OTPROM).
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Advance Information 183
EPROM/OTPROM
13.3 EPROM Registers
The EPROM programming register (EPROG) controls the actual programming of the EPROM bytes and the mask option register (MOR). The MOR controls eight mask options found on the read-only memory (ROM) version of this microcontroller unit (MCU). There is an additional EPROM bit (EPMSEC) located at the computer operating properly (COP) address to provide EPROM array security.
13.3.1 EPROM Programming Register The EPROM programming register (EPROG) shown in Figure 13-1 contains the control bits for programming the EPROM. In normal operation, the EPROM programming register contains all logic 0s.
Address: $001C Bit 7 Read: Write: Reset: 0 0 6 0 R 0 5 0 R 0 4 0 R 0 3 0 ELAT R 0 R 0 0 0 MPGM EPGM 2 1 Bit 0
= Unimplemented
= Reserved for test
Figure 13-1. EPROM Programming Register (EPROG) EPGM -- EPROM Programming Bit This read/write bit applies the voltage from the IRQ/VPP pin to the EPROM. To write the EPGM bit, the ELAT bit must already be set. Clearing the ELAT bit also clears the EPGM bit. Reset clears EPGM. 1 = EPROM programming power switched on 0 = EPROM programming power switched off MPGM -- Mask Option Register (MOR) Programming Bit This read/write bit applies programming power from the IRQ/VPP pin to the MOR. Reset clears MPGM. 1 = MOR programming power switched on 0 = MOR programming power switched off
Advance Information 184 EPROM/OTPROM
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EPROM/OTPROM EPROM Registers
ELAT -- EPROM Bus Latch Bit This read/write bit configures address and data buses for programming the EPROM array. EPROM data cannot be read when ELAT is set. Clearing the ELAT bit also clears the EPGM bit. Reset clears ELAT. 1 = Address and data buses configured for EPROM programming of the array. The address and data buses are latched in the EPROM array when a subsequent write to the array is made. Data in the EPROM array cannot be read. 0 = Address and data buses configured for normal operation Whenever the ELAT bit is cleared, the EPGM bit is also cleared. Both the EPGM and the ELAT bit cannot be set using the same write instruction. Any attempt to set both the ELAT and EPGM bit on the same write instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. To program a byte of EPROM, manipulate the EPROG register as follows: 1. Set the ELAT bit in the EPROG register. 2. Write the desired data to the desired EPROM address. 3. Set the EPGM bit in the EPROG register for the specified programming time, tEPGM. 4. Clear the ELAT and EPGM bits in the EPROG register.
13.3.2 Mask Option Register The mask option register (MOR) shown in Figure 13-2 is an EPROM byte that controls eight mask options. The MOR is unaffected by reset. The erased state of the MOR is $00. The options that can be programmed by the MOR are: 1. Port software programmable pulldown devices (enable or disable) 2. Startup delay after stop (16 or 4064 cycles) 3. Oscillator shunt resistor (2 M or open) 4. STOP instruction (enable or disable) 5. Low-voltage reset (enable or disable)
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EPROM/OTPROM
6. Port A external interrupt function (enable or disable) 7. IRQ trigger sensitivity (edge-triggered only or both edge- and level-triggered) 8. COP watchdog (enable or disable)
Address: $1FF1 Bit 7 Read: SWPDI Write: Reset: Erased: 0 0 0 Unaffected by reset 0 0 0 0 0 DELAY OSCRES SWAIT LVREN PIRQ LEVEL COPEN 6 5 4 3 2 1 Bit 0
Figure 13-2. Mask Option Register (MOR) SWPDI -- Software Pulldown Inhibit Bit This EPROM bit inhibits software control of the port A and port B pulldown devices. 1 = Software pulldown inhibited 0 = Software pulldown enabled DELAY -- Stop Startup Delay Bit This EPROM bit selects the number of bus cycles that must elapse before bus activity begins following a restart from the stop mode. 1 = Startup delay is 4064 bus cycles. 0 = Startup delay is 16 bus cycles.
CAUTION:
The 16-cycle delay option will work properly in devices with the internal low-power oscillator or with a steady external clock source. Check crystal/ceramic resonator specifications carefully before using the 16-cycle delay option with a crystal or ceramic resonator. OSCRES -- Oscillator Resistor Bit This EPROM bit configures the internal shunt resistor. 1 = Oscillator configured with 2 M3/4 shunt resistor 0 = Oscillator configured without a shunt resistor
Advance Information 186 EPROM/OTPROM
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
EPROM/OTPROM EPROM Registers
NOTE:
The optional oscillator resistor is NOT recommended for devices that use an external RC oscillator. For such devices, this bit should be left erased as a 0. SWAIT -- STOP Conversion to WAIT Bit This EPROM bit disables the STOP instruction and prevents inadvertently turning off the COP watchdog with a STOP instruction. When the SWAIT bit is set, a STOP instruction puts the MCU in halt mode. Halt mode is a wait-like low-power state. The internal oscillator and timer clock continue to run, but the CPU clock stops. When the SWAIT bit is clear, a STOP instruction stops the internal oscillator, the internal clock, the CPU clock, the timer clock, and the COP watchdog timer. 1 = STOP instruction converted to WAIT instruction 0 = STOP instruction not converted to WAIT instruction LVREN -- Low-Voltage Reset Enable Bit This EPROM bit enables the low-voltage reset (LVR) function. 1 = LVR function enabled 0 = LVR function disabled PIRQ -- Port A IRQ Enable Bit This EPROM bit enables the PA3-PA0 pins to function as external interrupt sources. 1 = PA3-PA0 enabled as external interrupt sources 0 = PA3-PA0 not enabled as external interrupt sources LEVEL -- External Interrupt Sensitivity Bit This EPROM bit makes the external interrupt inputs level-triggered as well as edge-triggered 1 = IRQ/VPP pin negative-edge triggered and low-level triggered; PA3-PA0 pins positive-edge triggered and high-level triggered 0 = IRQ/VPP pin negative-edge triggered only; PA3-PA0 pins positive-edge triggered only
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COPEN -- COP Watchdog Enable Bit This EPROM bit enables the COP watchdog. 1 = COP watchdog enabled 0 = COP watchdog disabled
13.3.3 EPROM Security Bit An EPROM programmable bit is provided at the location of the COP watchdog register at $1FF0 as shown in Figure 13-3. This bit allows control of access to the EPROM array. Any accesses of the EPROM locations will return undefined results when the EPMSEC bit is set. Refer to 13.4.2 EPMSEC Programming for programming instructions.
Address: $1FF0 Bit 7 Read: OPT Write: Reset: Erased: 0 -- -- = Unimplemented EPMSEC Unaffected by reset -- -- -- -- -- COPC 6 5 4 3 2 1 Bit 0
Figure 13-3. EPROM Security in COP and Security Register (COPR) EPMSEC -- EPROM Security1 This EPROM write-only bit enables the access to the EPROM array. 1 = Access to the EPROM array in non-user modes is denied. 0 = Access to the EPROM array in non-user modes is enabled.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users.
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EPROM/OTPROM EPROM Programming
13.4 EPROM Programming
A programming board is available from Motorola to download to the on-chip EPROM/OTPROM using the factory-provided programming software. Factory-provided software for programming the PEPROM is available on the World Wide Web at: http://www.motorola.com/mcu/ The programming software copies to the 6144-byte space located at EPROM addresses $0700-$1EFF and to the 16-byte space at addresses $1FF0-$1FFF which includes the mask option register at address $1FF1, and the security bit at address $1FF0.
NOTE:
To program the EPROM/OTPROM, MOR, or EPMSEC bits properly, the VDD voltage must be greater than 4.5 volts.
13.4.1 MOR Programming The contents of the MOR should be programmed using the programmer board. To program any bits in the MOR, the desired bit states must be written to the MOR address and then the MPGM bit in the EPROG register must be used. The following sequence will program the MOR: 1. Write the desired data to the MOR location ($1FF1). 2. Apply the programming voltage to the IRQ/VPP pin. 3. Set the MPGM bit in the EPROG. 4. Wait for the programming time, tMPGM. 5. Clear the MPGM bit in the EPROG. 6. Remove the programming voltage from the IRQ/VPP pin. Once the MOR bits have been programmed, some of the options may experience glitches in operation after removal of the programming voltage. It is recommended that the part be reset before trying to verify the contents of the user EPROM or the MOR itself.
NOTE:
The contents of the EPROM or the MOR cannot be accessed if the EPMSEC bit in the COPR register has been set.
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13.4.2 EPMSEC Programming The EPMSEC bit is programmable. To program the EPMSEC bit, the desired state must be written to the COP address and then the MPGM bit in the EPROG register must be used. The following sequence will program the EPMSEC bit: 1. Write the desired data to bit 7 of the COPR location ($1FF0). 2. Apply the programming voltage to the IRQ/VPP pin. 3. Set the MPGM bit in the EPROG. 4. Wait for the programming time, tMPGM. 5. Clear the MPGM bit in the EPROG. 6. Remove the programming voltage from the IRQ/VPP pin. Once the EPMSEC bit has been programmed to a logic 1, access to the contents of the EPROM and MOR in the expanded non-user modes will be denied. It is therefore recommended that the user EPROM and MOR in the part first be programmed and fully verified before setting the EPMSEC bit.
13.5 EPROM Erasing
MCUs with windowed packages permit EPROM erasing with ultraviolet light. Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of an EPROM bit is a logic 0.
NOTE:
Unlike many commercial EPROMs, an erased EPROM byte in the MCU will read as $00. All unused locations should be programmed as 0s.
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Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 14. Instruction Set
14.1 Contents
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 14.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 14.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . 195 14.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 196 14.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.5 14.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.2 Introduction
The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The
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high-order product is stored in the index register, and the low-order product is stored in the accumulator.
14.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative
14.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
14.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
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Instruction Set Addressing Modes
14.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
14.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
14.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used random-access memory (RAM) or input/output (I/O) location.
14.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE.
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Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
14.3.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.
14.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
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Instruction Set Instruction Types
14.4 Instruction Types
The MCU instructions fall into the following five categories: * * * * * Register/memory instructions Read-modify-write instructions Jump/branch instructions Bit manipulation instructions Control instructions
14.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 14-1. Register/Memory Instructions
Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
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14.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE:
Do not use read-modify-write operations on write-only registers. Table 14-2. Read-Modify-Write Instructions
Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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Instruction Set Instruction Types
14.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
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Table 14-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ/VPP Pin High Branch if IRQ/VPP Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR
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Instruction Set Instruction Types
14.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 14-4. Bit Manipulation Instructions
Instruction Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Mnemonic BCLR BRCLR BRSET BSET
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14.4.5 Control Instructions These instructions act on central processor unit (CPU) registers and control CPU operation during program execution. Table 14-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ/VPP Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA
WAIT
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Instruction Set Instruction Set Summary
14.5 Instruction Set Summary
Table 14-6. Instruction Set Summary (Sheet 1 of 7)
Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
.
Operation
Description
HINZC
Add with Carry
A (A) + (M) + (C)
--
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
A9 ii B9 dd C9 hh ll D9 ee ff E9 ff F9 AB ii BB dd CB hh ll DB ee ff EB ff FB A4 ii B4 dd C4 hh ll D4 ee ff E4 ff F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 dd
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
---- --
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
ff dd
Arithmetic Shift Right
b7 b0
C
----
ff
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
rr dd dd dd dd dd dd dd dd rr rr
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- REL REL
BCS rel BEQ rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1
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Cycles
2 3 4 5 4 3 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3
Effect on CCR
Operand
Address Mode
Opcode
Instruction Set
Table 14-6. Instruction Set Summary (Sheet 2 of 7)
Source Form
BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low
Description
HINZC
PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C Z = 0 PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 ---------- ---------- ---------- ---------- ---------- ----------
REL REL REL REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL
28 29 22 24 2F 2E
rr rr rr rr rr rr
Bit Test Accumulator with Memory Byte
(A) (M)
---- --
A5 ii B5 dd C5 hh ll D5 ee ff E5 ff F5 p 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? C Z = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel
Branch if bit n clear
PC (PC) + 2 + rel ? Mn = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
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Cycles
3 3 3 3 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5
Effect on CCR
Operand
Address Mode
Opcode
Instruction Set Instruction Set Summary
Table 14-6. Instruction Set Summary (Sheet 3 of 7)
Source Form Operation Description Cycles
5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 6 2 2 dd 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5
Effect on CCR HINZC
BRSET n opr rel
Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL
00 02 04 06 08 0A 0C 0E 21 10 12 14 16 18 1A 1C 1E
dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd dd dd dd dd dd dd dd
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
BSET n opr
Set Bit n
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSR rel
Branch to Subroutine Clear Carry Bit Clear Interrupt Mask
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C 0 I 0 M $00 A $00 X $00 M $00 M $00
----------
REL
AD
CLC CLI CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X
-------- 0 -- 0 ------
INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX
98 9A 3F 4F 5F 6F 7F
Clear Byte
---- 0
1--
Compare Accumulator with Memory Byte
(A) - (M)
----
A1 ii B1 dd C1 hh ll D1 ee ff E1 ff F1 33 43 53 63 73 dd
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
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Operand
rr ff ff
Address Mode
Opcode
Instruction Set
Table 14-6. Instruction Set Summary (Sheet 4 of 7)
Source Form
CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X
Operation
Description
HINZC
Compare Index Register with Memory Byte
(X) - (M)
----
1
IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
A3 ii B3 dd C3 hh ll D3 ee ff E3 ff F3 3A 4A 5A 6A 7A dd
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
---- --
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
---- --
A8 ii B8 dd C8 hh ll D8 ee ff E8 ff F8 3C 4C 5C 6C 7C dd
INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
---- --
ff
Unconditional Jump
PC Jump Address
----------
BC dd CC hh ll DC ee ff EC ff FC BD dd CD hh ll DD ee ff ED ff FD A6 ii B6 dd C6 hh ll D6 ee ff E6 ff F6
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Conditional Address
----------
Load Accumulator with Memory Byte
A (M)
---- --
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Cycles
2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 3 2 5 6 7 6 5 2 3 4 5 4 3
Effect on CCR
Operand
Address Mode
Opcode
Instruction Set Instruction Set Summary
Table 14-6. Instruction Set Summary (Sheet 5 of 7)
Source Form LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP
ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
HINZC
Load Index Register with Memory Byte
X (M)
---- --
IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH
AE ii BE dd CE hh ll DE ee ff EE ff FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA ii BA dd CA hh ll DA ee ff EA ff FA 39 49 59 69 79 36 46 56 66 76 9C dd ii dd
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff
dd
Logical Shift Right
0 b7 b0
C
---- 0
ff
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
11 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
---- --
Rotate Byte Left through Carry Bit
C b7 b0
----
ff dd
Rotate Byte Right through Carry Bit
C b7 b0
----
ff
Reset Stack Pointer
SP $00FF
----------
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Instruction Set
Advance Information 205
Cycles
2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5
Effect on CCR
Operand
Address Mode
Opcode
Instruction Set
Table 14-6. Instruction Set Summary (Sheet 6 of 7)
Source Form Operation Description
SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
HINZC
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX ii A2 B2 dd C2 hh ll D2 ee ff ff E2 F2 99 9B B7 dd C7 hh ll D7 ee ff E7 ff F7 8E BF dd CF hh ll DF ee ff EF ff FF A0 ii B0 dd C0 hh ll D0 ee ff E0 ff F0 2 3 4 5 4 3 2 2 4 5 6 5 4 2 4 5 6 5 4 2 3 4 5 4 3
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
Set Carry Bit Set Interrupt Mask
C 1 I 1
-------- 1 -- 1 ------
Store Accumulator in Memory
M (A)
---- --
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
---- --
Subtract Memory Byte from Accumulator
A (A) - (M)
----
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte
-- 1 ------
INH
83
10
Advance Information 206 Instruction Set
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Cycles
6
Effect on CCR
Operand
Address Mode
Opcode
Instruction Set Opcode Map
Table 14-6. Instruction Set Summary (Sheet 7 of 7)
Source Form Operation
Transfer Accumulator to Index Register
Description
HINZC
X (A) ----------
TAX TST opr TSTA TSTX TST opr,X TST ,X TXA
INH DIR INH INH IX1 IX INH
97 3D 4D 5D 6D 7D 9F dd
Test Memory Byte for Negative or Zero
(M) - $00
----------
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts
A (X)
----------
WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
-- ------ opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
INH
8F
Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
14.6 Opcode Map
See Table 14-7.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Instruction Set
Advance Information 207
Cycles
2 4 3 3 5 4 2 2
Effect on CCR
Operand
Address Mode
Opcode
Instruction Set
208 Instruction Set MOTOROLA
Advance Information MC68HC705JJ7 * MC68HC705JP7 -- REV 4
Table 14-7. Opcode Map
Bit Manipulation Branch DIR
MSB LSB
Read-Modify-Write DIR 3 INH 4
5 3
Control IX 7
6 5
Register/Memory IMM A
2
DIR 1
5 5
REL 2
3
INH 5
3
IX1 6
NEG
IX1 1
INH 8
9
INH 9
DIR B
3
EXT C
4
IX2 D
5
IX1 E
4
IX F
3
0
BRSET0
3 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2
MSB LSB
0 1 2 3 4 5 6 7 8 9 A B C D E F
BSET0
DIR 2 5
BRA
REL 2 3
NEG
DIR 1
NEGA
INH 1
NEGX
INH 2
NEG
IX 1
RTI
INH 6 2
SUB
IMM 2 2
SUB
DIR 3 3
SUB
EXT 3 4
SUB
IX2 2 5
SUB
IX1 1 4
SUB
IX 3
0 1 2 3 4 5 6 7 8 9 A B C D E F
BRCLR0
3
BCLR0
DIR 2 5
BRN
REL 3 1 11
RTS
INH 2
CMP
IMM 2 2
CMP
DIR 3 3
CMP
EXT 3 4
CMP
IX2 2 5
CMP
IX1 1 4
CMP
IX 3
BRSET1
3
BSET1
DIR 2 5
BHI
REL 3 1 5
MUL
INH 3 2 3 6 5 10
SBC
IMM 2 2
SBC
DIR 3 3
SBC
EXT 3 4
SBC
IX2 2 5
SBC
IX1 1 4
SBC
IX 3
BRCLR1
3
BCLR1
DIR 2 5
BLS
REL 2 3
COM
DIR 1 5
COMA
INH 1 3
COMX
INH 2 3
COM
IX1 1 6
COM
IX 1 5
SWI
INH 2
CPX
IMM 2 2
CPX
DIR 3 3
CPX
EXT 3 4
CPX
IX2 2 5
CPX
IX1 1 4
CPX
IX 3
BRSET2
3
BSET2
DIR 2 5
BCC
REL 2 3 REL 3
LSR
DIR 1
LSRA
INH 1
LSRX
INH 2
LSR
IX1 1
LSR
IX 2
AND
IMM 2 2
AND
DIR 3 3
AND
EXT 3 4
AND
IX2 2 5
AND
IX1 1 4
AND
IX 3
BRCLR2
3
BCLR2 BSET3
BCS/BLO
2 5 3 3 6 5
BIT
IMM 2 2
BIT
DIR 3 3
BIT
EXT 3 4
BIT
IX2 2 5
BIT
IX1 1 4
BIT
IX 3
DIR 2 5 DIR 2 5
BRSET3
3
BNE
REL 2 3
ROR
DIR 1 5
RORA
INH 1 3
RORX
INH 2 3
ROR
IX1 1 6
ROR
IX 5 2 2
LDA
IMM 2
LDA
DIR 3 4
LDA
EXT 3 5
LDA
IX2 2 6
LDA
IX1 1 5
LDA
IX 4
BRCLR3
3
BCLR3
DIR 2 5
BEQ
REL 2 3
ASR
DIR 1 5 DIR 1 5
ASRA
INH 1 3 INH 1 3
ASRX
INH 2 3 INH 2 3
ASR
IX1 1 6 IX1 1 6
ASR
IX 5 IX 5 1
TAX
INH 2 2 2
STA
DIR 3 3
STA
EXT 3 4
STA
IX2 2 5
STA
IX1 1 4
STA
IX 3
BRSET4
3
BSET4
DIR 2 5
BHCC BHCS
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ROL
DIR 1 5
ASL/LSL
1
CLC
INH 2 2
EOR
IMM 2 2
EOR
DIR 3 3
EOR
EXT 3 4
EOR
IX2 2 5
EOR
IX1 1 4
EOR
IX 3
REL 2 3 REL 2 3
BRCLR4
3
BCLR4
DIR 2 5
ROLA
INH 1 3
ROLX
INH 2 3
ROL
IX1 1 6
ROL
IX 5 1
SEC
INH 2 2
ADC
IMM 2 2
ADC
DIR 3 3
ADC
EXT 3 4
ADC
IX2 2 5
ADC
IX1 1 4
ADC
IX 3
BRSET5
3
BSET5
DIR 2 5
BPL
REL 2 3
DEC
DIR 1
DECA
INH 1
DECX
INH 2
DEC
IX1 1
DEC
IX 1
CLI
INH 2 2
ORA
IMM 2 2
ORA
DIR 3 3
ORA
EXT 3 4
ORA
IX2 2 5
ORA
IX1 1 4
ORA
IX 3
BRCLR5
3
BCLR5
DIR 2 5
BMI
REL 3 1 5 3 3 6 5
SEI
INH 2 2
ADD
IMM 2
ADD
DIR 3 2
ADD
EXT 3 3
ADD
IX2 2 4
ADD
IX1 1 3
ADD
IX 2
BRSET6
3
BSET6
DIR 2 5
BMC
REL 2 3
INC
DIR 1 4
INCA
INH 1 3
INCX
INH 2 3
INC
IX1 1 5
INC
IX 4 1
RSP
INH 2 2 6
JMP
DIR 3 5
JMP
EXT 3 6
JMP
IX2 2 7
JMP
IX1 1 6
JMP
IX 5
BRCLR6
3
BCLR6
DIR 2 5
BMS
REL 2 3
TST
DIR 1
TSTA
INH 1
TSTX
INH 2
TST
IX1 1
TST
IX 2 1
NOP
INH 2
BSR
REL 2 2
JSR
DIR 3 3
JSR
EXT 3 4
JSR
IX2 2 5
JSR
IX1 1 4
JSR
IX 3
BRSET7
3
BSET7
DIR 2 5
BIL
REL 3 1 5 3 3 6 5
STOP
INH 2 2 2
LDX
IMM 2
LDX
DIR 3 4
LDX
EXT 3 5
LDX
IX2 2 6
LDX
IX1 1 5
LDX
IX 4
BRCLR7
3
BCLR7
DIR 2
BIH
REL 2
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
IX1 1
CLR
IX 1
WAIT
INH 1
TXA
INH 2
STX
DIR 3
STX
EXT 3
STX
IX2 2
STX
IX1 1
STX
IX
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
MSB LSB LSB of Opcode in Hexadecimal 0
3
0
MSB of Opcode in Hexadecimal
5 Number of Cycles
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 15. Electrical Specifications
15.1 Contents
15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 211 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . . 215 DC Electrical Characteristics (3.0 Vdc). . . . . . . . . . . . . . . . . . 216
15.10 Analog Subsystem Characteristics (5.0 Vdc) . . . . . . . . . . . . . 217 15.11 Analog Subsystem Characteristics (3.0 Vdc) . . . . . . . . . . . . . 218 15.12 Control Timing (5.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 15.13 Control Timing (3.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 15.14 PEPROM and EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.15 SIOP Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.16 SIOP Timing (VDD = 3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.17 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Electrical Specifications
Advance Information 209
Electrical Specifications
15.2 Introduction
This section contains the electrical and timing specifications.
15.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Supply voltage Bootloader/self-check mode (IRQ/VPP pin only) Current drain per pin excluding VDD and VSS Operating junction temperature Storage temperature range Symbol VDD VIn I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to 17 25 +150 -65 to +150 Unit V V mA C C
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 15.8 DC Electrical Characteristics (5.0 Vdc) and 15.9 DC Electrical Characteristics (3.0 Vdc) for guaranteed operating conditions.
Advance Information 210
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Electrical Specifications MOTOROLA
Electrical Specifications Operating Temperature Range
15.4 Operating Temperature Range
Characteristic Operating temperature range Extended Symbol TA Value TL to TH -40 to +85 Unit C
15.5 Thermal Characteristics
Characteristic Thermal resistance Plastic DIP SOIC Symbol JA Value 60 Unit C/W
15.6 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc)
Characteristic(1) RUN(3) (analog and LVR disabled) Internal low-power oscillator at 100 kHz Internal low-power oscillator at 500 kHz External oscillator running at 4.2 MHz WAIT(4) (analog and LVR disabled) Internal low-power oscillator at 100 kHz Internal low-power oscillator at 500 kHz External oscillator running at 4.2 MHz STOP(5) (analog and LVR disabled) Typical -40 C to 85 C Incremental IDD for enabled modules LVR Analog subsystem Symbol Min Typ(2) 150 375 3.00 Max Unit A A mA A A mA A
IDD
-- -- --
568 1100 5.20
IDD
-- -- --
45 75 1.00
85 375 2.20
IDD
-- --
2 4
10 20
IDD
-- --
5 380
15 475
A
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL TA TH, unless otherwise noted. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25 C only 3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 4. Wait IDD is affected linearly by the OSC2 capacitance. 5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD -0.2 Vdc, OSC1 = VDD.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Electrical Specifications
Advance Information 211
Electrical Specifications
15.7 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc)
Characteristic(1) RUN(3) (analog and LVR disabled) Internal low-power oscillator at 100 kHz Internal low-power oscillator at 500 kHz External oscillator running at 2.1 MHz WAIT(4) (analog and LVR disabled) Internal low-power oscillator at 100 kHz Internal low-power oscillator at 500 kHz External oscillator running at 2.1 MHz STOP(5) (analog and LVR disabled) 25 C -40 C to 85 C Incremental IDD for enabled modules LVR Analog subsystem Symbol Min Typ(2) 70 320 1.25 Max Unit A A mA A A mA A
IDD
-- -- --
320 800 2.60
IDD
-- -- --
20 40 0.50
65 250 1.10
IDD
-- --
1 2
5 10
IDD
-- --
5 380
15 475
A
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 V, TL TA TH, unless otherwise noted. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25 C only. 3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 4. Wait IDD is affected linearly by the OSC2 capacitance. 5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD -0.2 Vdc, OSC1 = VDD.
Advance Information 212
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Electrical Specifications MOTOROLA
Electrical Specifications Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc)
3.50E-03 3.00E-03 SUPPLY CURRENT IN AMPS 2.50E-03 2.00E-03 1.50E-03 1.00E-03 5.00E-04 0.00E+00 0 0.5 1 1.5 2 2.5 FREQUENCY IN MHz 5.5 V 4.5 V 3.3 V 2.7 V
Figure 15-1. Typical Run IDD versus Internal Clock Frequency at 25 C
1.60E-03 1.40E-03 SUPPLY CURRENT IN AMPS 1.20E-03 1.00E-03 8.00E-04 6.00E-04 4.00E-04 2.00E-04 0.00E+00 0 0.5 1 1.5 2 2.5 FREQUENCY IN MHz 5.5 V 4.5 V 3.3 V 2.7 V
Figure 15-2. Typical Wait IDD versus Internal Clock Frequency at 25 C
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Electrical Specifications
Advance Information 213
Electrical Specifications
3.50E-03 SUPPLY CURRENT IN AMPS 3.00E-03 2.50E-03 2.00E-03 1.50E-03 1.00E-03 5.00E-04 2.5 -40 C 25 C 85 C
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE IN VOLTS
Figure 15-3. Typical Run IDD with External Oscillator
1.80E-03 1.60E-03 SUPPLY CURRENT IN AMPS 1.40E-03 1.20E-03 1.00E-03 8.00E-04 6.00E-04 4.00E-04 2.00E-04 2.5 3 3.5 4 4.5 5 5.5 6 SUPPLY VOLTAGE IN VOLTS -40 C 25 C 85 C
Figure 15-4. Typical Wait IDD with External Oscillator
4.50E-06 4.00E-06 3.50E-06 3.00E-06 2.50E-06 2.00E-06 1.50E-06 1.00E-06 5.00E-07 0.00E+00 2.5
SUPPLY CURRENT IN AMPS
-40 C 25 C 85 C
3
3.5
4 4.5 5 SUPPLY VOLTAGE IN VOLTS
5.5
6
Figure 15-5. Typical Stop IDD with Analog and LVR Disabled
Advance Information 214
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Electrical Specifications MOTOROLA
Electrical Specifications DC Electrical Characteristics (5.0 Vdc)
15.8 DC Electrical Characteristics (5.0 Vdc)
Characteristic(1), Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (ILoad = -0.8 mA) PB0-PB7 (ILoad = -4.0 mA) PA0-PA5, PB4, PC0-PC7 Output low voltage (ILoad = 1.6 mA) PB0-PB7, RESET (ILoad = 10 mA) PA0-PA5, PB4, PC0-PC7(4) (ILoad = 15 mA) PA0-PA5, PB4, PC0-PC7(4) High source current Total for all (6) PA0-PA5 pins and PB4 Total for all (8) PC0-PC7(4) pins High sink current Total for all (6) PA0-PA5 pins and PB4 Total for all (8) PC0-PC7(4) pins Input high voltage PA0-PA5, PB0-PB7, PC0-PC7(4), RESET, OSC1, IRQ/VPP Input low voltage PA0-PA5, PB0-PB7, PC0-PC7(4), RESET, OSC1, IRQ/VPP Input current OSC1, IRQ/VPP Input current RESET (pullup, source) RESET (pulldown, sink) I/O ports hi-Z leakage current (pulldowns off) PA0-PA6, PB0-PB7, PC0-PC7(4) Input pulldown current PA0-PA5, PB0-PB7, PC0-PC7(4) (VIn ; VIH = 0.7 x VDD) PA0-PA5, PB0-PB7, PC0-PC7
(4) (4) (2)
Symbol
Min
Typ(3)
Max
Unit
VOL VOH
-- VDD -0.1
-- --
0.1 --
V
VOH
VDD -0.8 VDD -0.8
-- --
-- --
V
VOL
-- -- --
-- -- --
0.4 0.4 1.5
V
IOH
-- --
-- --
20 30
mA
IOL
-- -- 0.7 x VDD
-- --
40 60 VDD
mA
VIH
-- --
V
VIL IIn
VSS -1
0.3 x VDD 1
V A
--
IIn
10 -6 -2
-- -- --
-- -- 2
A mA A
IOZ
IIL
(VIn ; VIL = 0.3 x VDD)
40 25
100 65
280 190
A
1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only. 4. PC0-PC7 parameters only apply to MC68HC705JP7.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Electrical Specifications
Advance Information 215
Electrical Specifications
15.9 DC Electrical Characteristics (3.0 Vdc)
Characteristic(1), Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (ILoad = -0.2 mA) PB0-PB7 (ILoad = -2.0 mA) PA0-PA5, PB4, PC0-PC7 Output low voltage (ILoad = 1.6 mA) PB0-PB7, RESET (ILoad = 5 mA) PA0-PA5, PB4, PC0-PC7 High source current Total for all (6) PA0-PA5 pins and PB4 Total for all (8) PC0-PC7(4) pins High sink current Total for all (6) PA0-PA5 pins and PB4 Total for all (8) PC0-PC7(4) pins Input high voltage PA0-PA5, PB0-PB7, PC0-PC7(4), RESET, OSC1, IRQ/VPP Input low voltage PA0-PA5, PB0-PB7, PC0-PC7(4), RESET, OSC1, IRQ/VPP Input current OSC1, IRQ/VPP Input current RESET (pullup, source) RESET (pulldown, sink) I/O ports hi-Z leakage current (pulldowns off) PA0-PA6, PB0-PB7, PC0-PC7(4) Input pulldown current PA0-PA5, PB0-PB7, PC0-PC7(4) (VIn ; VIH = 0.7 x VDD) PA0-PA5, PB0-PB7, PC0-PC7(4) (VIn ; VIL = 0.3 x VDD)
1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only. 4. PC0-PC7 parameters only apply to MC68HC705JP7.
(4) (4) (2)
Symbol
Min
Typ(3)
Max
Unit
VOL VOH
-- VDD -0.1
-- --
0.1 --
V
VOH
VDD -0.8 VDD -0.8
-- --
-- --
V
VOL
-- --
-- --
0.3 0.3
V
IOH
-- --
-- --
20 30
mA
IOL
-- -- 0.7 x VDD
-- --
40 60 VDD
mA
VIH
-- --
V
VIL IIn
VSS -1
0.2 x VDD 1
V A
--
IIn
5 -3 -2
-- -- --
-- -- 2
A mA A
IOZ
IIL
10 4
25 20
75 40
A
Advance Information 216
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Electrical Specifications MOTOROLA
Electrical Specifications Analog Subsystem Characteristics (5.0 Vdc)
15.10 Analog Subsystem Characteristics (5.0 Vdc)
NOTE:
See Figure 15-6.
Symbol Min Max Unit
Characteristic(1) Voltage comparators Input offset voltage Common-mode range Comparator 1 input impedance Comparator 2 input impedance Direct input to comparator 2 (HOLD = 1, DHOLD = 0) Divider input to comparator 2 (HOLD = 0, DHOLD = 1) Input divider ratio (comparator 2, HOLD = 0, DHOLD =1) VIn = 0 to VDD -1.5 V Analog subsystem internal VSS offset Sum of comparator offset and IR drop through VSS Channel selection multiplexer switch resistance External current source (PB0/AN0) Source current (VOut = VDD/2) Source current linearity (VOut = 0 to VDD -1.5 Vdc) Discharge sink current (VOut = 0.4 V) External capacitor (connected to PB0/AN0) Voltage range Discharge time Value of external ramping capacitor Internal sample and hold capacitor Capacitance Charge/discharge time (0 to 3.5 Vdc) Direct connection (HOLD = 1, DHOLD = 0) Divided connection (HOLD = 0, DHOLD = 1) Temperature diode connection (HOLD = 1, DHOLD = 1) Leakage discharge rate Internal temperature sensing diode Voltage at TJ = 25 C Temperature change in voltage
1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted
VIO VCMR ZIn ZIn ZIn RDIV VAOFF RMUX ICHG ICHG IDIS VCAP tDIS CEXT
-- -- 800 800 80 0.49
15 VDD -1.5 -- -- -- 0.51
mV V k k k
20 --
40 3
mV k A %FS mA
85 -- 1.1 VSS 5 -- 8 1 2 1 -- 0.65 1.8
113 1 -- VDD -1.5 10 2 13 -- -- -- 0.2 0.71 2.0
V ms/F F pF s s s V/sec V mV/ C
CSH tSHCHG tSHDCHG tSHTCHG CSHDIS VD TCD
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Electrical Specifications
15.11 Analog Subsystem Characteristics (3.0 Vdc)
NOTE:
See Figure 15-6.
Symbol Min Max Unit
Characteristic(1) Voltage comparators Input offset voltage Common-mode range Comparator 1 input impedance Comparator 2 input impedance Direct input to comparator 2 (HOLD = 1, DHOLD = 0) Divider input to comparator 2 (HOLD = 0, DHOLD = 1) Input divider ratio (comparator 2, HOLD = 0, DHOLD =1) VIn = 0 to VDD -1.5 V Analog subsystem internal VSS offset Multiplexer switch resistance External current source (PB0/AN0) Source current (VOut = VDD/2) Source current linearity (VOut = 0 to VDD -1.5 Vdc) Discharge sink current (VOut = 0.4 V) External capacitor (connected to PB0/AN0) Voltage range Discharge time Value of external ramping capacitor Internal sample and hold capacitor Capacitance Charge/discharge time (0 to 3.5 Vdc) Direct connection (HOLD = 1, DHOLD = 0) Divided connection (HOLD = 0, DHOLD = 1) Temperature diode connection (HOLD = 1, DHOLD = 1) Leakage discharge rate Internal temperature sensing diode Voltage at TJ = 25 C Temperature change in voltage
1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted
VIO VCMR ZIn ZIn ZIn RDIV VAOFF RMUX ICHG ICHG IDIS VCAP tDIS CEXT CSH tSHCHG tSHDCHG tSHTCHG CSHDIS VD TCD
-- -- 800 800 80 0.49 10 -- 75 -- 1
15 VDD -1.5 -- -- -- 0.51 30 5 104 1 --
mV V k k k
mV k A %FS mA
VSS 5 --
VDD -1.5 10 2
V ms/F F
8 1 2 1 -- 0.65 1.8
13 -- -- -- 0.1 0.71 2.0
pF s s s V/sec V mV/ C
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Electrical Specifications Analog Subsystem Characteristics (3.0 Vdc)
820 800 780 760 740 720 700 680 660 640 620 600 580 560 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 TEMPERATURE IN C
T DIODE IN mV
Figure 15-6. Typical Temperature Diode Performance
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Electrical Specifications
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Electrical Specifications
15.12 Control Timing (5.0 Vdc)
Characteristic(1) Frequency of oscillation (OSC) RC oscillator option Crystal oscillator option External clock source Internal low-power oscillator Standard product (100 kHz nominal) Mask option (500 kHz nominal, see Note 3) Internal operating frequency, crystal, or external clock (fOSC/2) RC oscillator option Crystal oscillator option External clock source Internal low-power oscillator Standard product (100 kHz nominal) Mask option (500 kHz nominal(2)) Cycle time (1/fOP) External oscillator or clock source Internal low-power oscillator Standard product (100 kHz nominal) Mask option (500 kHz nominal(2)) 16-bit timer Resolution Input capture (TCAP) pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width (external clock input) Analog subsystem response Voltage comparators Switching time (10 mV overdrive, either input) Comparator power-up delay (bias circuit already powered up) External current source (PB0/AN0) Switching time (IDIS to IRAMP) Power-up delay (bias circuit already powered up) Bias circuit power-up delay Symbol Min -- 0.1 dc 60 300 -- 0.05 dc 30 150 Max 4.2 4.2 4.2 140 700 2.1 2.1 2.1 75 350 Unit MHz MHz MHz kHz kHz MHz MHz MHz kHz kHz
fOSC
fOP
476 tcyc 14.29 2.86 tRESL tTH, tTL tILIH tILIL tOH, tOL 4.0 284 284
(3)
-- 33.33 6.67 -- -- -- -- --
ns s s tcyc ns ns tcyc ns
110
tCPROP tCDELAY tISTART tIDELAY tBDELAY
-- -- -- -- --
2 2 1 2 2
s s s s s
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL TA TH, unless otherwise noted 2. The 500-kHz nominal mask option is available through special order only. Contact your local Motorola sales representative for detailed ordering information. Not offered with the RC oscillator. 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc.
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Electrical Specifications Control Timing (3.0 Vdc)
15.13 Control Timing (3.0 Vdc)
Characteristic(1) Frequency of oscillation (OSC) RC oscillator option Crystal oscillator option External clock source Internal low-power oscillator Standard product (100 kHz nominal) Mask option (500 kHz nominal, see Note 3)) Internal operating frequency, crystal, or external clock (fOSC/2) RC oscillator option Crystal oscillator option External clock source Internal low-power oscillator Standard product (100 kHz nominal) Mask option (500 kHz nominal(2)) Cycle time (1/fOP) External oscillator or clock source Internal low-power oscillator Standard product (100 kHz nominal) Mask option (500 kHz nominal(2)) 16-bit timer Resolution Input capture (TCAP) pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width (external clock input) Analog subsystem response Voltage comparators Switching time (10 mV overdrive, either input) Comparator power-up delay (bias circuit already powered up) External current source (PB0/AN0) Switching time (IDIS to IRAMP) Power-up delay (bias circuit already powered up) Bias circuit power-up delay Symbol Min -- 0.1 dc 60 300 -- 0.05 dc 30 150 Max 2.1 2.1 2.1 140 700 1.05 1.05 1.05 70 350 Unit MHz MHz MHz kHz kHz MHz MHz MHz kHz kHz
fOSC
fOP
952 tcyc 14.29 2.86 tRESL tTH, tTL tILIH tILIL tOH, tOL 4.0 284 284
(3)
-- 33.33 6.67 -- -- -- -- --
ns s s tcyc ns ns tcyc ns
110
tCPROP tCDELAY tISTART tIDELAY tBDELAY
-- -- -- -- --
2 2 1 2 2
s s s s s
1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. The 500 kHz nominal mask option is available through special order only. Contact your local Motorola sales representative for detailed ordering information. Not offered with the RC oscillator option. 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc.
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Electrical Specifications
510000 500000 490000 FREQUENCY IN Hz 480000 470000 460000 450000 440000 430000 420000 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95
TEMPERATURE IN C
Figure 15-7. Typical 500 kHz External Low-Power Oscillator Frequency
114000 113500 FREQUENCY IN Hz 113000 112500 112000 111500 111000 110500 110000 109500 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 TEMPERATURE IN C
Figure 15-8. Typical 100 kHz External Low-Power Oscillator Frequency
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Electrical Specifications Control Timing (3.0 Vdc)
2.5 INTERNAL BUS FREQUENCY (MHz)
2
1.5 VDD = 5.5 V 1 VDD = 4.5 V
0.5
0 12.1 24.9 EXTERNAL RESISTOR VALUE (k) 49.9
Figure 15-9. Typical RC Oscillator Internal Operating Frequency Range versus Resistance for High VDD Operating Range at T = 25 C
2 INTERNAL BUS FREQUENCY (MHz)
1.5
VDD = 3.3 V VDD = 2.7 V
1
0.5
0 12.1 24.9 EXTERNAL RESISTOR VALUE (k) 49.9
Figure 15-10. Typical RC Oscillator Internal Operating Frequency Range versus Resistance for Low VDD Operating Range at T = 25 C
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Electrical Specifications
15.14 PEPROM and EPROM Programming Characteristics
Characteristic(1) PEPROM programming voltage (IRQ/VPP) PEPROM programming voltage (IRQ/VPP) PEPROM programming time per bit EPROM/MOR programming voltage (IRQ/VPP) EPROM/MOR programming current (IRQ/VPP) EPROM programming time per byte MOR programming time Symbol VPP IPP tEPGM VPP IPP tEPGM tMPGM Min 16.0 -- 4.0 16.0 -- 4.0 10.0 Typ 16.5 3.0 -- 16.5 3.0 -- -- Max 17.0 5.0 -- 17.0 5.0 -- -- Unit V mA ms V mA ms ms
1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted
NOTE:
To program the EPROM/OTPROM, MOR, or EPMSEC bits, the voltage on VDD must be greater than 4.5 volts.
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Electrical Specifications SIOP Timing (VDD = 5.0 Vdc)
15.15 SIOP Timing (VDD = 5.0 Vdc)
Characteristic(1) Frequency of operation Master Slave Cycle time Master Slave Clock (SCK) low time (fOP = 4.2 MHz) SDO data valid time SDO hold time SDI setup time SDI hold time Symbol fSIOP(M) fSIOP(S) tSCK(M) tSCK(M) tSCKL tV tHO tS tH Min Typ Max Unit
0.25 x fOP dc 4.0 x tcyc -- 952 -- 0 100 100
0.25 x fOP -- 4.0 x tcyc -- -- -- -- -- --
0.25 x fOP 1050 4.0 x tcyc 3.8 -- 200 -- -- --
kHz
s ns ns ns ns ns
1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted
tSCK tSCKL SCK tV tHO
SDO
MSB tS
BIT 1
LSB
SDI
MSB
VALID DATA tH
LSB
Figure 15-11. SIOP Timing Diagram
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Electrical Specifications
15.16 SIOP Timing (VDD = 3.0 Vdc)
Characteristic(1) Frequency of operation Master Slave Cycle time Master Slave Clock (SCK) low time (fOP = 2.1 MHz) SDO data valid time SDO hold time SDI setup time SDI hold time Symbol fSIOP(M) fSIOP(S) tSCK(M) tSCK(M) tSCKL tV tHO tS tH Min 0.25 x fOP dc 4.0 x tcyc -- 1905 -- 0 200 200 Typ 0.25 x fOP -- 4.0 x tcyc -- -- -- -- -- -- Max 0.25 x fOP 525 4.0 x tcyc 1.9 -- 400 -- -- -- Unit
kHz
s ns ns ns ns ns
1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted
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Electrical Specifications Reset Characteristics
15.17 Reset Characteristics
Characteristic(1) Low-voltage reset Rising recovery voltage Falling reset voltage LVR hysteresis POR recovery voltage(2) POR VDD slew rate(2) Rising(2) Falling(2) RESET pulse width (when bus clock active) RESET pulldown pulse width from internal reset SVDDR SVDDF tRL tRPD -- -- 1.5 3 -- -- -- -- 0.1 0.05 -- 4 V/s Symbol VLVRR VLVRF VLVRH VPOR Min Typ Max Unit
2.4 2.3 30 0
3.4 3.3 70 --
4.4 4.3 -- 100
V V mV mV
tCYC tCYC
1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. By design, not tested
RESET VOLTAGE IN VOLTS
4.5 4 3.5 3 2.5 -45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
TEMPERATURE IN C
Figure 15-12. Typical Falling Low Voltage Reset
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Electrical Specifications
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Electrical Specifications
OSC11 t RL RESET 4064 or 16 tcyc(2) INTERNAL CLOCK(3) INTERNAL ADDRESS BUS(3) INTERNAL DATA BUS(3)
1FFE
1FFF
NEW PCH
NEW PCL
NEW PCH
NEW PCL
Op code
Notes: 1. Represents the internal gating of the OSC1 pin 2. Normal delay of 4064 tcyc or short delay option of 16 tcyc 3. Internal timing signal and data information not available externally
Figure 15-13. Stop Recovery Timing Diagram
INTERNAL RESET1
RESET PIN tRPD INTERNAL CLOCK(3) INTERNAL ADDRESS BUS(3) INTERNAL DATA BUS(3)
4064 or 16 tcyc(2)
1FFE
1FFF
NEW PCH
NEW PCL
NEW PCH
NEW PCL
Notes: 1.Represents the internal reset from low-voltage reset, illegal opcode fetch or COP watchdog timeout 2.Only if reset occurs during normal delay of 4064 tCYC or short delay option of 16 tCYC for initial power-up or stop recovery. 3.Internal timing signal and data information not available externally
Figure 15-14. Internal Reset Timing Diagram
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Electrical Specifications Reset Characteristics
VDD
VLVRF
VLVRR
LOW VOLTAGE RESET
RESET PIN1 INTERNAL CLOCK3 INTERNAL ADDRESS BUS(3) INTERNAL DATA BUS(3)
tRPD
4064 or 16 t
(2)
cyc
1FFE
1FFF
NEW PCH
NEW PCL
NEW PCH
NEW PCL
Notes: 1. RESET pin pulled down by internal device 2 Only if LVR occurs during normal delay of 4064 tcyc or short delay option of 16 tcyc for initial power-up or stop recovery. 3 Internal timing signal and data information not available externally
Figure 15-15. Low-Voltage Reset Timing Diagram
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Electrical Specifications
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Electrical Specifications
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MC68HC705JJ7 * MC68HC705JP7 -- REV 4 Electrical Specifications MOTOROLA
Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 16. Mechanical Specifications
16.1 Contents
16.2 16.3 16.4 16.5 16.6 16.7 16.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 20-Pin Plastic Dual In-Line Package (Case 738) . . . . . . . . . . 232 20-Pin Small Outline Integrated Circuit (Case 751D) . . . . . . . 233 28-Pin Plastic Dual In-Line Package (Case 710) . . . . . . . . . . 233 28-Pin Small Outline Integrated Circuit (Case 751F) . . . . . . . 234 20-Pin Windowed Ceramic Integrated Circuit (Case 732) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 28-Pin Windowed Ceramic Integrated Circuit (Case 733A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
16.2 Introduction
The MC68HC705JJ7 is available in: * * * 20-pin plastic dual in-line package (PDIP) 20-pin small outline integrated circuit (SOIC) package 20-pin windowed ceramic package
The MC68HC705JP7 is available in: * * * 28-pin plastic dual in-line package (PDIP) 28-pin small outline integrated circuit (SOIC) package 28-pin windowed ceramic package
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Mechanical Specifications
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Mechanical Specifications
The following figures show the latest packages at the time of this publication. To make sure that you have the latest case outline specifications, contact one of the following: * * Local Motorola Sales Office World Wide Web at: http://www.motorola.com/mcu/
Follow World Wide Web on-line instructions to retrieve the current mechanical specifications.
16.3 20-Pin Plastic Dual In-Line Package (Case 738)
-A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0 15 0.51 1.01
B
1 10
C
L
-TSEATING PLANE
K M E G F D 20 PL 0.25 (0.010)
M
N J 20 PL 0.25 (0.010) TA
M
M
TB
M
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Mechanical Specifications 20-Pin Small Outline Integrated Circuit (Case 751D)
16.4 20-Pin Small Outline Integrated Circuit (Case 751D)
-A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
-B-
P 10 PL 0.010 (0.25)
M
B
M
1
10
D
20 PL
0.010 (0.25)
M
TA
S
B
S
J
F R X 45 C -TG
18 PL SEATING PLANE
K
M
16.5 28-Pin Plastic Dual In-Line Package (Case 710)
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
28
15
B
1 14
A N
C
L
H
G F D
K
SEATING PLANE
M
J
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Mechanical Specifications
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Mechanical Specifications
16.6 28-Pin Small Outline Integrated Circuit (Case 751F)
-A28 15 14X
-B1 14
P 0.010 (0.25)
M
B
M
28X D
0.010 (0.25)
M
T
A
S
B
S
M R X 45
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.32 0.23 0.13 0.29 0 8 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029
-T26X
C G K -TSEATING PLANE
F J
16.7 20-Pin Windowed Ceramic Integrated Circuit (Case 732)
NOTES: 1. LEADS WITHIN 0.010 DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS.
20 1
11 10
B A F C L
DIM A B C D F G H J K L M N
N H D
SEATING PLANE
G
K
J M
INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040
Advance Information 234
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Mechanical Specifications 28-Pin Windowed Ceramic Integrated Circuit (Case 733A)
16.8 28-Pin Windowed Ceramic Integrated Circuit (Case 733A)
28 15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION A AND B INCLUDE MENISCUS. 4. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
B
1 14
-A-
M L
N -T-
SEATING PLANE
C K G F D 28 PL 0.25 (0.010)
M
J
DIM A B C D F G J K L M N
INCHES MIN MAX 1.435 1.490 0.500 0.605 0.160 0.240 0.015 0.022 0.050 0.065 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15 _ 0.020 0.050
MILLIMETERS MIN MAX 36.45 37.84 12.70 15.36 4.06 6.09 0.38 0.55 1.27 1.65 2.54 BSC 0.20 0.30 3.17 4.06 15.24 BSC 0_ 15 _ 0.51 1.27
TA
M
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Mechanical Specifications
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Mechanical Specifications
Advance Information 236
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Advance Information -- MC68HC705JJ7/MC68HC705JP7
Section 17. Ordering Information
17.1 Contents
17.2 17.3 17.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 MC68HC705JJ7 Order Numbers . . . . . . . . . . . . . . . . . . . . . . 238 MC68HC705JP7 Order Numbers . . . . . . . . . . . . . . . . . . . . . .239
17.2 Introduction
This section contains instructions for ordering the various erasable programmable read-only memory (EPROM) versions of the MC68HC05JJ/JP Family of microcontrollers.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Ordering Information
Advance Information 237
Ordering Information
17.3 MC68HC705JJ7 Order Numbers
MC order numbers for the available 20-pin package types are shown here.
Package Type Plastic DIP(2) SOIC(3) CERDIP(4), (5) Plastic DIP SOIC CERDIP(5) Plastic DIP SOIC CERDIP(5) EPO Oscill. Type(1) XTAL XTAL XTAL RC RC RC XTAL XTAL XTAL LPO Freq. (kHz) 100 100 100 100 100 100 500 500 500 Operating Temperature Range -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C
Order Number
MC68HC705JJ7CP MC68HC705JJ7CDW MC68HC705JJ7S MC68HRC705JJ7CP MC68HRC705JJ7CDW MC68HRC705JJ7S MC68HC705SJ7CP MC68HC705SJ7CDW MC68HC705SJ7S
1. Crystal/ceramic resonator or RC oscillator 2. Plastic dual in-line package (P, case outline 738) 3. Small outline integrated circuit package (DW, case outline 751D) 4. Windowed ceramic dual in-line package (S, case outline 732) 5. CERDIP parts are only guaranteed at room temperature and are for evoluation purposes only.
Advance Information 238 Ordering Information
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
Ordering Information MC68HC705JP7 Order Numbers
17.4 MC68HC705JP7 Order Numbers
MC order numbers for the available 28-pin package types are shown here.
Package Type Plastic DIP(2) SOIC(3) CERDIP(4), (5) Plastic DIP SOIC CERDIP(5) Plastic DIP SOIC CERDIP(5) EPO Oscill. Type(1) XTAL XTAL XTAL RC RC RC XTAL XTAL XTAL LPO Freq. (kHz) 100 100 100 100 100 100 500 500 500 Operating Temperature Range -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C
Order Number
MC68HC705JP7CP MC68HC705JP7CDW MC68HC705JP7S MC68HRC705JP7CP MC68HRC705JP7CDW MC68HRC705JP7S MC68HC705SP7CP MC68HC705SP7CDW MC68HC705SP7S
1. Crystal/ceramic resonator or RC oscillator 2. Plastic dual in-line package (P, case outline 710) 3. Small outline integrated circuit package (DW, case outline 751F) 4. Windowed ceramic dual in-line package (S, case outline 733A) 5. CERDIP parts are only guaranteed at room temperature and are for evoluation purposes only.
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA Ordering Information
Advance Information 239
Ordering Information
Advance Information 240 Ordering Information
MC68HC705JJ7 * MC68HC705JP7 -- REV 4 MOTOROLA
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USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-303-675-2140 1-800-441-2447 TECHNICAL INFORMATION CENTER: 1-800-521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://www.motorola.com/semiconductors/
MC68HC705JJ7/D REV 4

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